MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 376

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

10.2.1 External Interface
MC68F375
REFERENCE MANUAL
voltage supply
Internal mem-
ory patch sig-
CMFI ground
erase enable
erase enable
Program and
Description
CMFI power
Block 0 pro-
Master pro-
erase high
gram and
gram and
nal to externally control program or erase operations to array block 0 (E
other pins: V
The CMFI EEPROM module uses external signals to provide some external control of
operations and provide power. These signals are listed in
supply
nals
INTPATCHB
MNEMONIC
SSF
Table 10-1 CMFI EEPROM Module External Signals
E
V
E
V
V
PEB0
PEE
DDF
SSF
PP
V
DD3F
Freescale Semiconductor, Inc.
CDR MoneT FLASH FOR THE IMB3 (CMFI)
For More Information On This Product,
and V
These signals signify that the current bus cycle will be provided by the internal
patch memory instead of the CMFI.
The CMFI EEPROM BIU will force an aborted access to the CMFI if any of the
four patch signals = “1” to remain synchronized with the IMB3.
Thus the CMFI will not assert the data, data transfer acknowledge or burst trans-
fer acknowledge if any of the internal memory patch signals = “1”.
This optional signal externally controls program or erase operation. To enable
these operations the signal should be at the logic "1” level, while a logic "0” level
disables these operations in the CMFI module. The E
down device to keep a logic "0” unless the pin is driven to a logic "1” and a digital
filter to protect from external noise. On the MC68F375, this signal is connected to
V
This optional signal will externally control program or erase operations to array
block 0. To enable these operations the signal should be at the logic “1” level,
while a logic “0” level disables these operations in the CMFI Module. This signal
may be generated by any desired method and must remain valid throughout the
program or erase software starting their respective operation. The E
include a pull down device to keep a logic “0” unless the pin is driven to a logic
"1” and a digital filter to protect from external noise. When not connected to E
this signal will be connected to V
To reduce noise in the read path no other circuits should be connected to the
CMFI V
supply pin. This V
vice.
To reduce noise in the read path no other circuits should be connected to the
CMFI V
V
device. The specified voltage range during operation is 3. 0 V to 3. 6 V.
V
operations of the CMFI Module. A maximum of 2 CMFI Modules may be connect-
ed to a V
the V
DD
DDF
PP
provides the high voltage (4. 75 V to 5. 25 V) used during program and erase
to allow program and erase operations at all times.
DD
supply pin. This V
Go to: www.freescale.com
PP
SSF
DDF
voltage during all operations except program and erase.
PP
provide power to the module.
supply. A maximum of 2 CMFI Modules may be connected to a V
supply pin. The suggested voltage at the V
supply pin. A maximum of 2 CMFI Modules may be connected to a
Rev. 25 June 03
SSF
pin must be isolated from all other V
DDF
pin must be isolated from all other V
DD
Comments
to allow program and erase operations.
Table
10-1.
PEE
PP
signal includes a pull
pin should be equal to
SS
pins inside the de-
DD
PEB0
pins inside the
MOTOROLA
PEB0
). Three
pin will
PEB0
10-6
SSF