MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 393

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

10.5.2 Program Page Buffers
10.6 Operation
MC68F375
REFERENCE MANUAL
Each access to the CMFI EEPROM array shall determine if the requested location is
within the current burst buffers. If the requested location is not within the read burst
buffers then the correct read burst buffer shall be made invalid and a new 32 byte block
of information will be fetched from the array. The burst buffer address is updated and
status is made valid. If the requested location is within one of the current burst buffers
or has been fetched from the array the selected bytes are transferred to the IMB3 com-
pleting the access. While bursting data from the read burst buffer the address is
incremented by width of the internal data bus. Upon reaching the end of the read burst
buffer the CMFI EEPROM shall terminate the burst access.
The CMFI EEPROM can program up to eight 64-byte pages at one time. Each pro-
gram page buffer is associated with one array block as indicated in the diagrams in
Figure
IADDR[14|13:6], stored in the BIU. The block offset address is extracted from the
address of the first programming write. To select the CMFI EEPROM array block that
will be programmed, the program page buffers use the CMFI EEPROM array configu-
ration and BLOCK[7:0]. The data programmed in each array block is determined by
the programming writes to the program buffer for each block. All program buffer data
is unique whereas the program page offset address is shared by all blocks.
The array block that will be programmed is selected by the BLOCK bit that is a 1. If
BLOCK[M] = 1 then program buffer[M] is active and array block[M] will program. If
BLOCK[M] = 0 then program buffer[M] is inactive and array block[M] will not program.
Bits in the program page buffers shall select the non-program state if SES = 0. During
a program margin read, the program buffers will update bits to the non-program state
for bits that correspond to array bits that the program margin read has determined are
programmed.
The following sections describe the functioning of the CMFI EEPROM during various
operational modes. The primary function of the CMFI EEPROM Module is to serve as
electrically erasable and programmable non-volatile memory accessed by any bus
master capable of using the IMB3.
• Setting/Clearing PBR
• Reset,
• Programming write
• Erase interlock write
• Setting EHV
• Clearing SES
• Setting/Clearing SIE
10-1. All program page buffers share the same block offset address,
Freescale Semiconductor, Inc.
CDR MoneT FLASH FOR THE IMB3 (CMFI)
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
MOTOROLA
10-23