MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 163

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

CSOR0 — Chip-Select Option Registers
CSOR3
CSOR5
CSOR6
CSOR7
CSOR8
CSOR9
CSOR10
MC68F375
REFERENCE MANUAL
MOD
MSB
Bit(s)
14:13
12:11
15
E
9:6
0
15
10
RESET:
CSORBT and CSOR[0], [3] and [5:10] contain parameters that support operations
from external memory devices. Bit and field definitions for CSORBT and CSOR[0], [3]
and [5:10] are the same.
14
BYTE[1:0]
0
DSACK
MODE
Name
BYTE
STRB
R/W
13
0
Asynchronous/Synchronous Mode. In asynchronous mode, chip-select assertion is synchro-
nized with AS and DS.
0 = Asynchronous mode is selected.
1 = Synchronous mode is selected, and used with ECLK peripherals.
Upper/lower byte option. This field is used only when the chip-select 16-bit port option is
selected in the pin assignment register. This allows the usage of two external 8-bit memory
devices to be concatenated to form a 16-bit memory.
00 = Disable
01 = Lower byte
10 = Upper byte
11 = Both bytes
Read/write. This field causes a chip select to be asserted only for a read, only for a write, or for
both reads and writes.
00 = Disable
01 = Read only
10 = Write only
11 = Read/Write
Address strobe/data strobe. This bit controls the timing for assertion of a chip select in asynchro-
nous mode only. Selecting address strobe causes the chip select to be asserted synchronized
with address strobe. Selecting data strobe causes the chip select to be asserted synchronized
with data strobe. Data strobe timing is used to create a write strobe when needed.
0 = Address strobe
1 = Data strobe
Data strobe acknowledge. This field specifies the source of DSACK in asynchronous mode as
internally generated or externally supplied. It also allows adjust bus timing adjustment with
internal DSACK generation by controlling the number of wait states that are inserted to optimize
bus speed in a particular application.
termination encoding (0b1110) effectively corresponds to –1 wait states.
12
0
R/W[1:0]
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
11
0
For More Information On This Product,
Table 4-37 CSOR Bit Descriptions
STRB
10
0
Go to: www.freescale.com
9
0
Rev. 25 June 03
DSACK[3:0]
8
0
Table 4-38
7
0
Description
6
0
shows the DSACK[3:0] field encoding. The fast
SPACE[1:0]
5
0
4
0
3
0
IPL[2:0]
2
0
0xYF FA5A
0xYF FA6A
0xYF FA4E
0xYF FA6E
0xYF FA62
0xYF FA66
0xYF FA72
0xYF FA76
MOTOROLA
1
0
AVEC
LSB
4-81
0
0