MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 69

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

3.8.1 M68000 Family Compatibility
3.8.2 Special Control Instructions
3.8.2.1 Low-Power Stop (LPSTOP)
3.8.2.2 Table Lookup and Interpolate (TBL)
3.8.2.3 Loop Mode Instruction Execution
MC68F375
REFERENCE MANUAL
It is the philosophy of the M68000 family that all user-mode programs can execute
unchanged on future derivatives of the M68000 family. Supervisor-mode programs
and exception handlers should require only minimal alteration.
The CPU32 can be thought of as an intermediate member of the M68000 Family.
Object code from an MC68000 or MC68010 may be executed on the CPU32. Many of
the instruction and addressing mode extensions of the MC68020 are also supported.
Refer to the CPU32 Reference Manual (CPU32RM/AD) for a detailed comparison of
the CPU32 and MC68020 instruction set.
Low-power stop (LPSTOP) and table lookup and interpolate (TBL) instructions have
been added to the MC68000 instruction set for use in controller applications.
In applications where power consumption is a consideration, the CPU32 forces the
device into a low-power standby mode when immediate processing is not required.
The low-power stop mode is entered by executing the LPSTOP instruction. The pro-
cessor remains in this mode until an unmasked interrupt or reset occurs.
To maximize throughput for real-time applications, reference data is often precalcu-
lated and stored in memory for quick access. Storage of many data points can require
an inordinate amount of memory. The table lookup instruction requires that only a
sample of data points be stored, reducing memory requirements. The TBL instruction
recovers intermediate values using linear interpolation. Results can be rounded with a
round-to-nearest algorithm.
The CPU32 has several features that provide efficient execution of program loops.
One of these features is the DBcc looping primitive instruction. To increase the perfor-
mance of the CPU32, a loop mode has been added to the processor. The loop mode
is used by any single word instruction that does not change the program flow. Loop
mode is implemented in conjunction with the DBcc instruction.
required form of an instruction loop for the processor to enter loop mode.
Freescale Semiconductor, Inc.
For More Information On This Product,
CENTRAL PROCESSOR UNIT
Go to: www.freescale.com
Rev. 25 June 03
Figure 3-7
MOTOROLA
shows the
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