MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 155

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.8.4 Interrupt Processing Summary
4.9 Chip Selects
MC68F375
REFERENCE MANUAL
A summary of the entire interrupt processing sequence follows. When the sequence
begins, a valid interrupt service request has been detected and is pending.
Typical microcontrollers require additional hardware to provide chip-select signals for
external devices. The SCIM2E includes nine programmable chip-select circuits that
can provide from 2- to 16-clock cycle access to external memory and peripherals.
Address block sizes of two Kbytes to one Mbyte can be selected.
gram of a basic system that uses chip selects.
1. The CPU32 finishes higher priority exception processing or reaches an instruc-
2. Processor state is stacked.
3. The interrupt acknowledge cycle begins:
4. Modules or external peripherals that have requested interrupt service decode
5. After arbitration, the interrupt acknowledge cycle is completed in one of the fol-
6. The vector number is converted to a vector address.
7. The content of the vector address is loaded into the PC and the processor
a. FC[2:0] are driven to 0b111 (CPU space) encoding.
b. The address bus is driven as follows. ADDR[23:20] = 0b1111
c. Request priority is latched into the CCR IP field from the address bus.
a. When there is no contention (responding modules have IARB = 0b0000),
b. The interrupt source that wins arbitration supplies a vector number and
c. The AVEC signal is asserted either by the external device requesting
d. The bus monitor or external device asserts BERR and the CPU32
tion boundary.
the priority value in ADDR[3:1]. Each module or device with a request level
equal to the value in ADDR[3:1] enters interrupt arbitration.
lowing ways:
transfers control to the exception handler routine.
ADDR[19:16] = 0b1111, which indicates that the cycle is an interrupt
acknowledge CPU space cycle; ADDR[15:4] = 0b111111111111;
ADDR[3:1] = the priority of the interrupt request being acknowledged; and
ADDR0 = 0b1.
the internal bus monitor, if enabled, asserts BERR, and the CPU32
generates the spurious interrupt vector number.
DSACK signals appropriate to the access. The CPU32 acquires the
vector number.
interrupt service (AVEC can be tied low if all external interrupts are to use
autovectors) or by an appropriately programmed SCIM2E chip select, and
the CPU32 generates an autovector number corresponding to the
interrupt priority.
generates the spurious interrupt vector number.
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
Figure 4-21
MOTOROLA
is a dia-
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