MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 118

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.5.1.11 Autovector Signal
4.5.2 Dynamic Bus Sizing
MC68F375
REFERENCE MANUAL
The autovector signal (AVEC) can be used to terminate interrupt acknowledgment
cycles for external interrupts only. Assertion of AVEC causes the CPU32 to generate
vector numbers to locate an interrupt handler routine. If AVEC is continuously
asserted, autovectors are generated for all external interrupt requests. AVEC is
ignored during all other bus cycles. Refer to
for external interrupt requests can also be supplied internally by chip-select logic.
Refer to
when there is an external bus master. Refer to
more information.
The MCU dynamically interprets the port size of an addressed device during each bus
cycle, allowing operand transfers to or from 8-bit and 16-bit ports.
During a bus transfer cycle, an external device signals its port size and indicates com-
pletion of the bus cycle to the MCU through the use of the DSACK inputs, as shown in
Table
nal device. Refer to
If the CPU is executing an instruction that reads a long-word operand from a 16-bit
port, the MCU latches the first 16 bits of valid data and then runs another bus cycle to
obtain the other 16 bits. The operation for an 8-bit port is similar, but requires four read
cycles. The addressed device uses the DSACK signals to indicate the port width. For
instance, a 16-bit external device always returns DSACK for a 16-bit port (regardless
of whether the bus cycle is a byte or word operation).
Dynamic bus sizing requires that the portion of the data bus used for a transfer to or
from a particular port size be fixed. A 16-bit port must reside on data bus bits [15:0],
and an 8-bit port must reside on data bus bits [15:8]. This minimizes the number of bus
cycles needed to transfer data and ensures that the MCU transfers valid data.
The MCU always attempts to transfer the maximum amount of data on all bus cycles.
For a word operation, it is assumed that the port is 16 bits wide when the bus cycle
begins.
Operand bytes are designated as shown in
of access. For instance, OP0 is the most significant byte of a long-word operand, and
is accessed first, while OP3, the least significant byte, is accessed last. The two bytes
4-19. Chip-select logic can generate data size acknowledge signals for an exter-
4.9 Chip Selects
DSACK1
1
1
0
0
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
4.9 Chip Selects
Table 4-19 Effect of DSACK Signals
For More Information On This Product,
DSACK0
1
0
1
0
for more information. The autovector function is disabled
Go to: www.freescale.com
Rev. 25 June 03
Insert wait states in current bus cycle
Complete cycle — Data bus port size is 8 bits
Complete cycle — Data bus port size is 16 bits
Reserved
for more information.
4.8 Interrupts
Figure
4.6.6 External Bus Arbitration
4-10. OP[0:3] represent the order
Result
for more information. AVEC
MOTOROLA
4-36
for