MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 332

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

CANCTRL0 — Control Register 0
7.8.3 Control Register 0
MC68F375
REFERENCE MANUAL
BOFF
MSB
MSK
15
Bit(s)
15:11
Bit(s)
13:12
11:10
0
10:8
RESET:
7:5
4:0
9:8
7:0
15
14
ERR
MSK
14
0
CANCTRL1
ILCAN[2:0]
BOFFMSK
RXMODE
IVBA[2:0]
ERRMSK
TXMODE
Name
Name
RESERVED
—
—
—
13
0
12
0
Reserved
When the TouCAN generates an interrupt request, ILCAN[2:0] determines which of the inter-
rupt request signals is asserted. When a request is acknowledged, the TouCAN compares
ILCAN[2:0] to a mask value supplied by the CPU32 to determine whether to respond.
ILCAN[2:0] must have a value in the range of 0x0 (interrupts disabled) to 0x7 (highest
priority).
The interrupt vector base address specifies the high-order three bits of all the vector num-
bers generated by the different TouCAN interrupt sources.
Reserved
Bus off interrupt mask. The BOFF MASK bit provides a mask for the bus off interrupt.
0 = Bus off interrupt disabled.
1 = Bus off interrupt enabled.
Error interrupt mask. The ERRMSK bit provides a mask for the error interrupt.
0 = Error interrupt disabled.
1 = Error interrupt enabled.
Reserved
Receive pin configuration control. These bits control the configuration of the CANRX0 and
CANRX1 pins. Refer to the
Transmit pin configuration control. This bit field controls the configuration of the CANTX0 and
CANTX1 pins. Refer to
See
Table
Freescale Semiconductor, Inc.
11
0
RXMOD
Table 7-13 CANCTRL0 Bit Settings
For More Information On This Product,
Table 7-12 CANICR Bit Settings
7-16.
CAN 2.0B CONTROLLER MODULE
10
0
Go to: www.freescale.com
TXMODE
9
0
Rev. 25 June 03
Table
Table
8
0
7-15.
7-14.
7
0
Description
Description
6
0
5
0
CANCTRL1
4
0
3
1
2
0
0xYF F086
MOTOROLA
1
0
LSB
7-26
0
0