MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 123

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.6.3 Fast Termination Cycles
MC68F375
REFERENCE MANUAL
When an external device can meet fast access timing, the fast termination option of
SCIM2E chip selects can provide a two-cycle external bus transfer. Because the chip-
select circuits are driven from the system clock, bus cycle termination is inherently syn-
chronized with the system clock.
If multiple chip selects are to be used to provide control signals to a single device and
match conditions can occur simultaneously, all MODE, STRB, and associated DSACK
fields must be programmed to the same value. This prevents a conflict on the internal
bus when the wait states are loaded into the DSACK counter shared by all chip-
selects.
ASSERT DS AND WAIT FOR DSACK (S3)
TERMINATE OUTPUT TRANSFER (S5)
1) NEGATE DS AND AS
2) REMOVE DATA FROM DATA BUS
1) SET R/W TO WRITE
2) DRIVE ADDRESS ON ADDR[23:0]
3) DRIVE FUNCTION CODE ON FC[2:0]
4) DRIVE SIZ[1:0] FOR OPERAND SIZE
PLACE DATA ON DATA[15:0] (S2)
START NEXT CYCLE
OPTIONAL STATE (S4)
ADDRESS DEVICE (S0)
ASSERT AS (S1)
NO CHANGE
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
MCU
For More Information On This Product,
Figure 4-12 Write Cycle Flowchart
Go to: www.freescale.com
Rev. 25 June 03
1) DECODE ADDRESS, R/W, SIZ[1:0], DS
2) LATCH DATA FROM DATA BUS
3) ASSERT DSACK SIGNALS
ACCEPT DATA (S2 + S3)
TERMINATE CYCLE
NEGATE DSACK
PERIPHERAL
WR CYC FLOW
MOTOROLA
4-41