MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 64

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

3.7 Privilege Levels
3.8 Instructions
MC68F375
REFERENCE MANUAL
tion. Exception processing can be forced externally by an interrupt, a bus error, or a
reset.
The background processing state is initiated by breakpoints, execution of special
instructions, or a double bus fault. Background processing is enabled by pulling BKPT
low during RESET. Background processing allows interactive debugging of the sys-
tem via a simple serial interface.
The processor operates at one of two levels of privilege: user or supervisor. Not all
instructions are permitted to execute at the user level. All instructions are available at
the supervisor level. Effective use of privilege level can protect system resources from
uncontrolled access. The state of the S bit in the status register determines the privi-
lege level and whether the user stack pointer (USP) or supervisor stack pointer (SSP)
is used for stack operations.
The CPU32 instruction set is summarized in
CPU32 is very similar to that of the MC68020. Two new instructions have been added
to facilitate controller applications: low-power stop (LPSTOP) and table lookup and
interpolate (TBLS, TBLSN, TBLU, TBLUN).
Table 3-1
The CPU32 traps on unimplemented instructions or illegal effective addressing
modes, allowing user-supplied code to emulate unimplemented capabilities or to
define special purpose functions. However, Motorola reserves the right to use all cur-
rently unimplemented instruction operation codes for future M68000 core
enhancements.
CALLM, RTM
PACK, UNPK
Instruction
CAS, CAS2
Memory
cpxxx
BFxx
shows the MC68020 instructions that are not implemented on the CPU32.
Bit Field Instructions (BFCHG, BFCLR, BFEXTS, BFEXTU, BFFFO, BFINS, BFSET, BFTST)
Call Module, Return Module
Coprocessor Instructions (cpBcc, cpDBcc, cpGEN)
Pack, Unpack BCD Instructions
Memory Indirect Addressing Modes
Compare and Swap (Read-Modify-Write Instructions)
Table 3-1 Unimplemented MC68020 Instructions
Freescale Semiconductor, Inc.
For More Information On This Product,
CENTRAL PROCESSOR UNIT
Go to: www.freescale.com
Rev. 25 June 03
Description
Table
3-2. The instruction set of the
MOTOROLA
3-10