MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 381

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
Bit(s)
9:8
13
12
11
10
BOOT
Name
LOCK
EMUL
ASPC
SIE
Table 10-4 CMFIMCR Bit Settings (Continued)
Shadow information enable. The SIE bit is write protected by the start end sequence (SES)
bit for programming operation. Writes will have no effect if SES = 1 and PE = 0. The SIE bit
can be read whenever the registers are enabled.
When an array location is read in this mode, the shadow information will be read from a loca-
tion determined by the column, 32-byte read page select, and word addresses (IADDR[7:0])
of the access. Accessing the CMFI control block registers will access the registers and not
the shadow information. The default reset state of SIE is normal array access (SIE = 0).
The address range of the shadow information is the entire address range of the CMFI
EEPROM array but the high order array addresses, IADDR[17|16|15:7], are not used to
encode the location. The first 32 bytes (IADDR[7:0] = 0x00 to 0x1F) of the 256 bytes of
shadow locations are withheld by Motorola for the register shadow information words. The
remaining 224 bytes are available for general use. This is shown in
The upper address bits (IADDR[7:6]) are forced to 0 during reset. When SIE = 1, only the
program page buffer associated with the lowest block can be programmed. The other pro-
gram page buffers cannot be accessed and will not apply any programming voltages to their
CMFI array blocks while programming the shadow information. The shadow information is
typically in block 0 except for when the 192K-byte and 96K-byte arrays are mapped high,
then the shadow information is in block 2.
0 = Normal array access.
1 = Disables normal array access and selects the shadow information.
Boot control. After reset, the BOOT bit may be cleared or set via a write to CMFIMCR; how-
ever, it will not affect bootstrap operation. If the STOP bit is set (STOP = 1) then bootstrap
operation will be terminated. While the CMFI EEPROM is configured to provide the bootstrap
information and read access to the control block, the CMFI array will not provide correct data.
Control block writes will not be affected by bootstrap operation.
0 = The CMFI will respond to bootstrap address after reset.
1 = The CMFI will not respond to bootstrap address after reset.
Lock control. In normal operation once the LOCK bit is asserted (LOCK = 0) the write-lock
can only be disabled again by a master reset. The LOCK bit is writable if the device is in
background debug mode (IFREEZEB = 0).
When the LOCK control bit in the CMFIMCR register is asserted (LOCK = 0) the write-lock
register bits ASPC, WAIT, PROTECT, EMUL and CMFIBAH are locked. Writes to these bits
will have no effect.
Read always, clear once unless in background debug mode.
0 = Write-locked registers are protected.
1 = Write-lock is disabled.
Emulation operation. When the EMUL control bit in the CMFIMCR register is a 1, the CMFI
EEPROM is placed in emulation operation. Emulation operation may be entered by writing
EMUL to a 1 on devices that support emulation operation; otherwise, writes have no opera-
tional effect. The state of this bit after master reset is the logical NOR of EMULIN and
EMULEN, EMUL = EMULIN and EMULEN. Emulation operation allows the array to be emu-
lated externally, with access controlled by the CMFI EEPROM.
Array space. The array may be specified to exist in supervisor or unrestricted space. The
default reset state of ASPC is programmed in a CMFI EEPROM shadow bit by the user.
ASPC may be written by the bus master any time STOP = 1 and LOCK = 1. The ASPC bits
govern accesses to the array, but have no effect on how control registers and shadow reg-
isters are accessed.
00 = Unrestricted data space (IFC = x01), unrestricted program space (IFC = x10)
01 = Unrestricted program space (IFC = x10)
10 = Supervisor data space (IFC = 101), supervisor program space (IFC = 110)
11 = Supervisor program space (IFC = 110)
Freescale Semiconductor, Inc.
CDR MoneT FLASH FOR THE IMB3 (CMFI)
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
Description
Figure
10-3.
MOTOROLA
10-11