MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 108

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.4.5 Spurious Interrupt Monitor
4.4.6 Software Watchdog
MC68F375
REFERENCE MANUAL
the halt monitor (HME) enable bit in SYPCR. Refer to
more information.
During interrupt exception processing, the CPU32 normally acknowledges an interrupt
request, arbitrates among various sources of interrupt, recognizes the highest priority
source, and then acquires a vector or responds to a request for autovectoring. The
spurious interrupt monitor asserts the internal bus error signal (BERR) if no interrupt
arbitration occurs during interrupt exception processing. The assertion of BERR
causes the CPU32 to load the spurious interrupt exception vector into the program
counter. The spurious interrupt monitor cannot be disabled.
Refer to
exception processing, refer to
The software watchdog is controlled by the software watchdog enable (SWE) bit in
SYPCR. When enabled, the watchdog requires that a service sequence be written to
the software service register (SWSR) on a periodic basis. If servicing does not take
place, the watchdog times out and asserts the RESET signal.
Each time the service sequence is written, the software watchdog timer restarts. The
sequence to restart the software watchdog requires the following steps:
Both writes must occur before timeout in the order listed. Any number of instructions
can be executed between the two writes.
The clock rate of the watchdog timer is affected by clock mode, the software watchdog
prescale (SWP) bit, and the software watchdog timing (SWT[1:0]) field in SYPCR. In
slow reference mode and external clock mode, f
the watchdog timer. The options in fast reference mode are f
512. In all cases, the divide-by-512 option is selected when SWP = 1.
The value of SWP is affected by the state of the V
as shown in
SWT[1:0] selects the divide ratio used to establish the software watchdog timeout
period.
• Write 0x55 to SWSR
• Write 0xAA to SWSR
4.8 Interrupts
Table
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
4-11. System software can change SWP value.
Freescale Semiconductor, Inc.
For More Information On This Product,
for further information. For detailed information about interrupt
Table 4-11 SWP Reset States
1 (Synthesized Clock)
V
0 (External Clock)
DDSYN
Go to: www.freescale.com
4.8.1 Interrupt Exception
/MODCLK
Rev. 25 June 03
1 ( 512)
ref
0 ( 1)
SWP
DDSYN
or f
4.6.5.2 Double Bus Faults
ref
Processing.
/MODCLK pin during reset,
512 can be used to clock
ref
128 or (f
ref
MOTOROLA
128)
4-26
for