MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 193

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

5.10.2 Queue Boundary Conditions
MC68F375
REFERENCE MANUAL
When the QADC64 encounters a CCW with the pause bit set, the queue enters the
paused state after completing the conversion specified in the CCW with the pause bit.
The pause flag is set and a pause software interrupt may optionally be issued. The sta-
tus of the queue is shown to be paused, indicating completion of a subqueue. The
QADC64 then waits for another trigger event to again begin execution of the next
subqueue.
The following are queue operation boundary conditions:
Boundary conditions also exist for combinations of pause and end-of-queue. One case
is when a pause bit is in one CCW and an end-of-queue condition is in the next CCW.
The conversion specified by the CCW with the pause bit set completes normally. The
pause flag is set. However, since the end-of-queue condition is recognized, the com-
pletion flag is also set and the queue status becomes idle, not paused. Examples of
this situation include:
• The first CCW in a queue contains channel 63, the end-of-queue (EOQ) code.
• BQ2 (beginning of queue 2) is set at the end of the CCW table (63) and a trigger
• BQ2 is set to CCW0 and a trigger event occurs on queue 1. After reading CCW0,
• BQ2 (beginning of queue 2) is set beyond the end of the CCW table (64–127) and
• The pause bit is set in CCW5 and the channel 63 (EOQ) code is in CCW6.
• The pause bit is set in CCW63.
• During queue 1 operation, the pause bit is set in CCW14 and BQ2 points to
The queue becomes active and the first CCW is read. The end-of-queue is rec-
ognized, the completion flag is set, and the queue becomes idle. A conversion is
not performed.
event occurs on queue 2.
The end-of-queue condition is recognized, a conversion is performed, the com-
pletion flag is set, and the queue becomes idle.
the end-of-queue condition is recognized, the completion flag is set, and the
queue becomes idle. A conversion is not performed.
a trigger event occurs on queue 2. Refer to
(QACR2)
mediately, the completion flag is set, and the queue becomes idle. A conversion
is not performed.
CCW15.
Multiple end-of-queue conditions may be recognized simultaneously,
although there is no change in the QADC64 behavior. For example,
if BQ2 is set to CCW0, CCW0 contains the EOQ code, and a trigger
event occurs on queue 1, the QADC64 reads CCW0 and detects
both end-of-queue conditions. The completion flag is set for queue 1
only and it becomes idle.
for information on BQ2. The end-of-queue condition is recognized im-
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
5.12.5 QADC64 Control Register 0 (QACR0)
Rev. 25 June 03
NOTE
5.12.7 QADC64 Control Register 2
MOTOROLA
on BQ2.
5-17