MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 236

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

6.3 Signal Descriptions
6.4 Memory Map
MC68F375
REFERENCE MANUAL
The QSMCM has 12 external pins, as shown in
use for their submodule function, can be used as general-purpose I/O port pins. The
RXDx and TXDx pins can alternately serve as general-purpose input-only and output-
only signals, respectively. ECK is a dedicated clock pin that is not usable on the
MC68F375.
For detailed descriptions of QSMCM signals, refer to
isters,
The QSMCM memory map, shown in
QSPI and dual SCI control and status registers, and the QSPI RAM. The QSMCM
memory map can be divided into supervisor-only data space and assignable data
space. The address offsets shown are from the base address of the QSMCM module.
Refer to
IMB3*
6.7.3 QSPI
Figure 1-2
*Note: SBIU Bus and interface to IMB3 are each 16 bits wide.
Pins, and
Freescale Semiconductor, Inc.
for a diagram of the MC68F375 internal memory map.
QUEUED SERIAL MULTI-CHANNEL MODULE
For More Information On This Product,
Figure 6-1 QSMCM Block Diagram
Receive and Transmit Queue
QSPI QUEUE RAM
6.8.6 SCI
Go to: www.freescale.com
Rev. 25 June 03
QSPI
SBIU
DSCI
SCI1
SCI2
Pins.
Table
6-1, includes the global registers, the
Figure
6.6 QSMCM Pin Control Reg-
6-1. Seven of the pins, if not in
2
7
2
SCK/QGPIO6
TXD2/QGPO2
PCS0/SS/QGPIO0
PCS1/QGPIO1
PCS2/QGPIO2
PCS3/QGPIO3
RXD1/QGPI1
RXD2/QGPI2
MISO/QGPIO4
MOSI/QGPIO5
TXD1/QGPO1
MOTOROLA
ECK
6-2