MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 133

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.6.6.1 Show Cycles
MC68F375
REFERENCE MANUAL
indicating that no other bus master is active. This technique allows the processing of
bus requests during data transfer cycles.
BG is negated a few clock cycles after BGACK transition. However, if bus requests are
still pending after BG is negated, the MCU asserts BG again within a few clock cycles.
This additional BG assertion allows external arbitration circuitry to select the next bus
master before the current master has released the bus.
Refer to
shows BR negated at the same time BGACK is asserted. Refer to the
ence Manual (SCIMRM/AD)
The MCU normally performs internal data transfers without affecting the external data
bus, but it is possible to show these transfers during debugging. AS is not asserted
externally during show cycles.
Show cycles are controlled by SHEN[1:0] in SCIMMCR. This field set to 0b00 by reset.
When show cycles are disabled, the address bus, function codes, size, and read/write
signals reflect internal bus activity, but AS and DS are not asserted externally and
external data bus pins are in a high-impedance state during internal accesses. Refer
to
more information.
4.2.5 Show Internal Cycles
RE-ARBITRATE OR RESUME PROCESSOR
1) NEGATE BG (AND WAIT FOR
1) ASSERT BUS GRANT (BG)
BGACK TO BE NEGATED)
Figure 4-16
TERMINATE ARBITRATION
Figure 4-16 Bus Arbitration Flowchart for Single Request
GRANT BUS ARBITRATION
OPERATION
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
MCU
which shows bus arbitration for a single device. The flow chart
For More Information On This Product,
for more information on bus arbitration.
Go to: www.freescale.com
and the
Rev. 25 June 03
SCIM Reference Manual (SCIMRM/AD)
1) PERFORM DATA TRANSFERS (READ AND
1) EXTERNAL ARBITRATION DETERMINES
2) NEXT BUS MASTER WAITS FOR BGACK
3) NEXT BUS MASTER ASSERTS BGACK
4) BUS MASTER NEGATES BR
1) ASSERT BUS REQUEST (BR)
1) NEGATE BGACK
WRITE CYCLES) ACCORDING TO THE SAME
RULES THE PROCESSOR USES
NEXT BUS MASTER
TO BE NEGATED
TO BECOME NEW MASTER
ACKNOWLEDGE BUS MASTERSHIP
RELEASE BUS MASTERSHIP
OPERATE AS BUS MASTER
REQUESTING DEVICE
REQUEST THE BUS
BUS ARB FLOW
SCIM Refer-
MOTOROLA
4-51
for