MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 410

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

RAMMCR1 — SRAM Module Configuration Register
RAMMCR2
RAMMCR3
RAMMCR4
RAMMCR
RESET:
11.3.2 Array Base Address Registers (RAMBAH, RAMBAL)
MC68F375
REFERENCE MANUAL
STOP
Bit(s)
14:13
MSB
15
9:8
7:0
15
12
11
10
1
The array base address registers are provided to allow the flexibility of placing the
SRAM array anywhere in the memory map. RAMBAH and RAMBAL contains an
address field used to specify the most significant bits of the lowest address value in
RESERVED
RASP[1:0]
14
0
Name
STOP
RLCK
PDS
—
—
—
13
0
Stop control. The assertion of the STOP control bit in the RAMMCR register by a bus master sig-
nals the SRAM module to enter into the STOP state. When STOP is asserted, SRAM array
accesses are ignored. When the SRAM module is in normal mode of operation the array base
address registers are write protected.
0 = SRAM module normal operation.
1 = Causes SRAM module to enter low power stop mode.
Reserved
Power down status. PDS is a optional status bit in the RAMMCR that enables a power monitor
for the SRAM array. The power monitor circuit will clear the PDS bit (PDS = “0”) if the array
standby power is lost. If the PDS bit is unimplemented reads will return “0”.
0 = Power monitor for the SRAM array is disabled. SRAM array standby power has failed.
1 = Power monitor for the SRAM array is enabled. SRAM array standby power has not failed.
Base address lock.
0 = SRAM base address registers are writable from the IMB3.
1 = SRAM base address registers are write locked.
Reserved
Array space. The RASP field limits access to the SRAM array to one of four CPU32 address
spaces. See
0 = Only the module configuration register, test register, and interrupt register are designated as
1 = All module registers and tables are designated as supervisor-only data space.
Reserved
PDS RLCK
12
0
supervisor-only data space. Access to all other locations is unrestricted.
Freescale Semiconductor, Inc.
STATIC RANDOM ACCESS MEMORY (SRAM)
RASP[1:0]
11
0
For More Information On This Product,
Table 11-1 RAMMCR Bit Settings
Table
00
01
10
11
Table 11-2 RASP Encoding
10
0
0
11-2.
Go to: www.freescale.com
Unrestricted program and data
Unrestricted program
Supervisor program and data
Supervisor program
RASP[1:0]
9
1
Rev. 25 June 03
8
1
Space
7
0
Description
6
0
5
0
RESERVED
4
0
3
0
2
0
0xYF FB00
0xYF F840
0xYF F848
0xYF F850
0xYF F858
MOTOROLA
1
0
11-4
LSB
0
0