MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 146

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.7.8.3 Single-Chip Mode
MC68F375
REFERENCE MANUAL
In the simpler of these two circuits, a resistor is connected in series with a diode from
the data bus pin to the RESET line. A bipolar transistor can be used for the same pur-
pose, but an additional current limiting resistor must be connected between the base
of the transistor and the RESET pin. If a MOSFET is substituted for the bipolar tran-
sistor, only the 1 K isolation resistor is required.
When BERR = 0 at the release of RESET, single-chip operation is selected. BERR
must return to a logic 1 before the first bus cycle after reset to insure proper device
operation. The external bus interface is essentially disabled in single-chip mode, and
SCIM2E pins generally serve as discrete inputs and outputs. The behavior of specific
pin groups is discussed in the following paragraphs.
ADDR[2:0] have no discrete I/O function in single-chip mode. These pins are placed
in a high-impedance state at power-on but can be enabled by clearing the ABD bit in
SCIMMCR.
ADDR[18:11] become port A input/output pins PA[7:0], and ADDR[10:3] become port
B input/output pins PB[7:0]. Each port is configurable entirely as inputs or outputs on
a per port basis by the DDA and DDB bits in the port A/B data direction register
(DDRAB).
Special attention should be paid to chip-select pins in single-chip mode. While each
chip-select base address register and option register is active and may be pro-
grammed as desired, a match condition will not assert the corresponding pin. For this
reason, chip selects should be used expressly to provide autovector termination of
interrupt acknowledge cycles generated in response to assertion of the IRQ[7:1] pins.
Figure 4-20 Alternate Circuit for Data Bus Mode Select Conditioning
The paragraphs that follow describe the behavior of SCIM2E pins in
single-chip mode only. Sections that follow cover 16-bit and 8-bit
expanded modes.
DATA PIN
RESET
1N4148
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
1 k
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
NOTE
ALTERNATE DATA BUS CONDITION CIRCUIT
DATA PIN
RESET
2 k
1 k
2N3906
MOTOROLA
4-64