MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 140

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.7.7 Pin State During Reset
4.7.7.1 Reset States of SCIM2E Pins
MC68F375
REFERENCE MANUAL
NOTES:
CYCLES
1. TWO CLOCK CYCLE DELAY REQUIRED BY RESET CONTROL LOGIC TO SWITCH RESET PIN FROM INPUT TO OUTPUT.
2. RESET CONTROL LOGIC DRIVES THE RESET PIN LOW FOR 512 CLOCK CYCLES TO GUARANTEE THIS LENGTH OF RESET TO THE ENTIRE SYSTEM.
3. TEN CLOCK CYCLE DELAY DURING WHICH THE RESET PIN IS NO LONGER DRIVEN AND IS ALLOWED TO RISE TO A LOGIC ONE. OPERATING
4. ADDITIONAL 180 CLOCK DELAY PROVIDED BY RESET CONTROL LOGIC TO ALLOW THE RESET PIN TO RISE TO A LOGIC ONE IF IT DID NOT DO SO DURING
5. INTERNAL START-UP TIME.
6. FIRST INSTRUCTION FETCHED.
CLKOUT
BUS
RESET
CONFIGURATION IS
THE PRIOR 10 CLOCK CYCLES.
LOCK
VCO
cycles take. Worst case occurs in slow reference mode and is approximately 15 milli-
seconds. During this period, MCU pins may be in an indeterminate state. While pull-
up resistors may be used on input only pins, active logic will be required to condition
input/output or output only pins.
Figure 4-18
V
It is important to keep the distinction between pin function and pin electrical state clear.
Although control register values and mode select inputs determine pin function, a pin
driver can be active, inactive, or in a high impedance state when reset occurs. During
power-on reset, pin state is subject to the constraints discussed in
Reset.
Generally, while RESET is asserted, SCIM2E pins either go into a high-impedance
state or are driven to their inactive states. Operating mode selection occurs when
DD
BUS STATE
UNKNOWN
LATCHED FROM DATA[15:0] AND BERR WHEN THIS DELAY BEGINS.
Pins that are not used should either be configured as outputs (if pos-
sible) or as inputs and be pulled to an appropriate inactive state. This
decreases unnecessary current consumption caused by digital
inputs floating near mid-supply level.
depicts the timing of the power-on reset sequence.
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
1
For More Information On This Product,
Figure 4-18 Power-On Reset
CONTROL SIGNALS
2
THREE-STATED
ADDRESS AND
Go to: www.freescale.com
Rev. 25 June 03
3
NOTE
4
5
4.7.6 Power-On
SCIM2E POR TIM
MOTOROLA
4-58
6