MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 147

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
Because match conditions do not result in chip-select assertion, the 0b10 (8-bit port)
and 0b11 (16-bit port) encodings of the pin assignment fields in CSPAR0 and CSPAR1
serve only to drive pins so configured high at all times. Consequently, any chip select
may provide autovector termination, even if its pin assignment field in CSPAR0 or
CSPAR1 is programmed with the 0b00 (discrete output) or 0b01 (alternate function)
encoding.
The first chip select that should be used for autovector termination in single-chip mode
is CSBOOT; it has no discrete output or alternate function capability. Although typically
not needed in single-chip mode, the SCIM2E bus arbitration feature may be used
when the BR/CS0, BG/CSM, and BGACK/CSE pins are configured for their alternate
functions. Of these three pins, only BR/CS0 can provide autovector termination. The
CSM and CSE chip selects function in emulation mode only and are not user
programmable.
CSPAR0 initially configures the SCIM2E function code pins FC[2:0] as port C discrete
outputs PC[2:0]. Each pin may, however, still operate as a function code output, and
when configured as such, will be driven during appropriate bus cycles. The chip-select
functions of FC0/CS3/PC0 and FC2/CS5/PC2 may also be used for autovector termi-
nation in the fashion described above.
ADDR[22:19]/CS[9:6]/PC[6:3] are initially configured as port C discrete outputs
PC[6:3] by chip-select pin assignment register 1 (CSPAR1). Each pin may, however,
still operate as an address line, and when configured as such, will be driven during
appropriate bus cycles.
CSPAR1 initially configures ADDR23/CS10/ECLK as a 16-bit chip select (0b11 pin
assignment field encoding) to drive the pin to its inactive state. ADDR23/CS10/ECLK
has no discrete output function. When 0b00 is programmed into its pin assignment
field in CSPAR1, ADDR23/CS10/ECLK will drive the M6800 bus E clock signal.
Just as the chip-select, function code, and bus arbitration signals associated with port
C can be made active in single-chip mode, so too can the bus control signals associ-
ated with port E. While initially configured as discrete I/O by the port E pin assignment
register (PEPAR), any port E bus control signal can be made active and will be driven
or accept input during appropriate bus cycles.
Port F pins will initially be configured for discrete I/O in single-chip mode but can oth-
erwise serve as interrupt request lines or edge-detect I/O pins with optional interrupt
capability. Because no external bus is available in single-chip mode, interrupt requests
from port F pins configured as interrupts (as opposed to interrupt requests from the
port F edge-detect logic) must have their interrupt acknowledge cycles terminated by
autovector.
In single-chip mode, the data bus is disabled at all times. DATA[15:8] become port G
input/output pins PG[7:0], and DATA[7:0] become port H input/output pins PH[7:0].
Port G and H pins are configurable as inputs or outputs on a per pin basis.
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
MOTOROLA
4-65