MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 282

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
Bit(s)
15:9
8
7
6
5
4
3
RDRF
Name
TDRE
IDLE
RAF
OR
TC
—
Transmit data register empty. TDRE is set when the byte in TDRx is transferred to the transmit
serial shifter. If this bit is zero, the transfer is yet to occur and a write to TDRx will overwrite the
previous value. New data is not transmitted if TDRx is written without first clearing TDRE.
0 = Transmit data register still contains data to be sent to the transmit serial shifter.
1 = A new character can now be written to the transmit data register.
For transmit queue operation, this bit should be ignored by software.
Transmit complete. TC is set when the transmitter finishes shifting out all data, queued pream-
bles (mark/idle-line), or queued breaks (logic zero).
0 = SCI transmitter is busy.
1 = SCI transmitter is idle.
For transmit queue operation, TC is cleared when SCxSR is read with TC set, followed by a write
to SCTQ[0:15].
Receive data register full. RDRF is set when the contents of the receive serial shifter are trans-
ferred to register RDRx. If one or more errors are detected in the received word, the appropriate
flag(s) (NF, FE, or PF) are set within the same clock cycle.
0 = Receive data register is empty or contains previously read data.
1 = Receive data register contains new data.
For receiver queue operation, this bit should be ignored by software.
Receiver active flag. RAF indicates whether the receiver is busy. This flag is set when the
receiver detects a possible start bit and is cleared when the chosen type of idle line is detected.
RAF can be used to reduce collisions in systems with multiple masters.
0 = SCI receiver is idle.
1 = SCI receiver is busy.
Idle line detected. IDLE is set when the receiver detects an idle-line condition (reception of a min-
imum of 10 or 11 consecutive ones as specified by ILT in SCCxR1). This bit is not set by the idle-
line condition when RWU in SCCxR1 is set. Once cleared, IDLE is not set again until after RDRF
is set (after the line is active and becomes idle again). If a break is received, RDRF is set, allow-
ing a subsequent idle line to be detected again.
Under certain conditions, the IDLE flag may be set immediately following the negation of RE in
SCCxR1. System designs should ensure this causes no detrimental effects.
0 = SCI receiver did not detect an idle-line condition.
1 = SCI receiver detected an idle-line condition.
For receiver queue operation, IDLE is cleared when SCxSR is read with IDLE set, followed by a
read of SCRQ[0:15].
Overrun error. OR is set when a new byte is ready to be transferred from the receive serial shifter
to register RDRx, and RDRx is already full (RDRF is still set). Data transfer is inhibited until OR
is cleared. Previous data in RDRx remains valid, but additional data received during an overrun
condition (including the byte that set OR) is lost.
Note that whereas the other receiver status flags (NF, FE, and PF) reflect the status of data
already transferred to RDRx, the OR flag reflects an operational condition that resulted in a loss
of data to RDRx.
0 = RDRF is cleared before new data arrives.
1 = RDRF is not cleared before new data arrives.
Reserved
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
For More Information On This Product,
Table 6-25 SCxSR Bit Settings
Go to: www.freescale.com
Rev. 25 June 03
Description
MOTOROLA
6-48