MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 382

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

10.4.4 CMFI EEPROM Test Register (CMFITST)
CMFITST — CMFI EEPROM Test Register
MC68F375
REFERENCE MANUAL
MSB
Bit(s)
NOTES:
15
7:6
5:0
0
The CMFI EEPROM test register is used to control the test operation of the CMFI
EEPROM array and BIU. Only 6 bits are read/writeable in the CMFITST register (in
supervisor mode only).
1. The NVR, STE, and GDB bits are not accessible in all revisions of the MC68F375 (prior to the J61X mask set).
2. The PAWS bits are not accessible in all revisions of the MC68F375.
3. The STE bit should always be programmed as a 0.
Shadow information words and locations withheld by Motorola for future applications.
General use special MoneT shadow information.
RESERVED
14
0
Name
WAIT
—
If a CMFI EEPROM enables the lock protection mechanism (LOCK
= 0) before PROTECT is cleared the device must use background
debug mode (IFREEZEB = 0) to program or erase the CMFI
EEPROM.
13
0
Table 10-4 CMFIMCR Bit Settings (Continued)
12
Wait states. The WAIT field is used to specify the number of wait states inserted by the BIU
during accesses. These wait states are added to the bus cycle between the IMB3 asserting
data strobe (IDSB) and the CMFI EEPROM writing or reading data. For burst accesses, the
wait states are inserted for the first data access only. A wait state has a duration of one sys-
tem clock cycle. This feature allows the migration of storage space from a slower emulation
or development system memory to the MC68F375 without the need for re-timing the system.
The program and erase margin reads will extend the bus cycle to their respective timings
regardless of the value of WAIT. Read always, writable if LOCK = 1.
00 = Minimum bus cycles = 3 clocks, 1 inserted wait states
01 = Minimum bus cycles = 4 clocks, 2 inserted wait states
10 = Minimum bus cycles = 5 clocks, 3 inserted wait states
11 = Minimum bus cycles = 2 clocks, 0 inserted wait states
Reserved
0
Freescale Semiconductor, Inc.
NVR
11
CDR MoneT FLASH FOR THE IMB3 (CMFI)
For More Information On This Product,
0
Figure 10-3 Shadow Information
1
256 Bytes of Special MoneT Shadow Information
10
0
Go to: www.freescale.com
Address Range, IADDR[7:0]
PAWS
9
0
Rev. 25 June 03
Figure 10-2
2
WARNING
8
0
RESERVED STE
Description
7
0
6
0
1,3
GDB
5
0
1
4
0
3
0
RESERVED
0xYF F804
2
0
MOTOROLA
1
0
10-12
LSB
0
0