MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 128

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.6.4.2 LPSTOP Broadcast Cycle
4.6.5 Bus Exception Control Cycles
MC68F375
REFERENCE MANUAL
Low power stop mode is initiated by the CPU32. Individual modules can be stopped
by setting the STOP bits in each module configuration register. The SCIM2E can turn
off system clocks after execution of the LPSTOP instruction. When the CPU32 exe-
cutes LPSTOP, a low power stop broadcast cycle is generated. The SCIM2E brings
the MCU out of low power mode when either a reset or an interrupt of higher priority
than the interrupt mask level in the CPU32 condition code register occurs.
Refer to
UNIT
During an LPSTOP broadcast cycle, the CPU32 performs a CPU space write to
address 0x3FFFE. This write puts a copy of the interrupt mask value in the clock con-
trol logic. The mask is encoded on the data bus as shown in
The LPSTOP CPU space cycle is shown externally (if the bus is available) as an indi-
cation to external devices that the MCU is going into low power stop mode. The
SCIM2E provides an internally generated DSACK response to this cycle. The timing
of this bus cycle is the same as for a fast termination write cycle. If the bus is not avail-
able (arbitrated away), the LPSTOP broadcast cycle is not shown externally.
An external device or a chip-select circuit must assert at least one of the DSACK[1:0]
signals or the AVEC signal to terminate a bus cycle normally. Bus exception control
cycles are used when bus cycles are not terminated in the expected manner.
Acceptable bus cycle termination sequences are summarized as follows. The case
numbers refer to
termination.
• Normal Termination
• Halt Termination
• Bus Error Termination
— DSACK is asserted; BERR and HALT remain negated (case 1).
— HALT is asserted at the same time or before DSACK, and BERR remains
— BERR is asserted in lieu of, at the same time as, or before DSACK (case 3),
for more information.
negated (case 2).
Figure 4-15 LPSTOP Interrupt Mask Encoding on DATA[15:0]
4.3.8.6 Low Power Operation
BERR assertion during the LPSTOP broadcast cycle is ignored.
15
0
14 13 12 11 10
0
Table
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
0
For More Information On This Product,
0
4-21, which indicates the results of each type of bus cycle
0
Go to: www.freescale.com
0
Rev. 25 June 03
9
0
8
0
7
0
NOTE
and
6
0
SECTION 3 CENTRAL PROCESSOR
5
0
4
0
LPSTOP MASK LEVEL
3
0
2
IP MASK
Figure
1
0
4-15.
MOTOROLA
4-46