MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 169

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.10 General-Purpose Input/Output
MC68F375
REFERENCE MANUAL
The SCIM2E has six general-purpose input/output ports: A, B, E, F, G, and H. (Port C,
an output-only port, is included under the discussion of chip-selects). Ports A, B, and
G are available in single-chip mode only and port H is available in single-chip and 8-
bit expanded modes only. Ports E, F, G, and H have associated data direction regis-
ters to configure each port pin as an input or output. Ports A and B share a data
direction register that configures each port entirely as inputs or outputs. Ports E and F
have associated pin assignment registers that allow the digital I/O or alternate function
of each port pin to be selected. Port F has an edge-detect flag register that indicates
whether a transition has occurred on any of its pins.
Table 4-42
modes in which they are available.
Access to the port A, B, E, G, and H data and data direction registers, and the port E
pin assignment register require three clock cycles to ensure timing compatibility with
external port replacement logic. Accesses to the port F registers require two clock
cycles. Port registers are byte-addressable and are grouped to allow coherent word
access to port data register pairs A-B and G-H, as well as word aligned long-word
coherency of the port A-B-G-H data registers.
shows the shared functions of the general-purpose I/O ports and the
Port
G
H
A
B
E
F
Table 4-41 CSBOOT Base and Option Register
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
Table 4-42 General-Purpose I/O Ports
Async/sync mode
Upper/lower byte
Address space
For More Information On This Product,
Base address
Read/write
Autovector
Block size
DSACK
AS/DS
Fields
IPL
IRQ[7:1]/FASTREF
Bus control signals
Shared Function
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ADDR[18:11]
ADDR[10:3]
DATA[15:8]
DATA[7:0]
Reset Values
Rev. 25 June 03
External vector externally
Asynchronous mode
Supervisor space
Reset Values
13 wait states
Both bytes
Read/write
0x000000
Any level
1 Mbyte
AS
Single-chip, 8-bit expanded
Single-chip
Single-chip
Single-chip
Modes
All
All
MOTOROLA
4-87