MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 79

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
MICROSEQUENCER
The serial interface uses a full-duplex synchronous protocol similar to the serial periph-
eral interface (SPI) protocol. The development system serves as the master of the
serial link since it is responsible for the generation of DSCLK. If DSCLK is derived from
the CPU32 system clock, development system serial logic is unhindered by the oper-
ating frequency of the target processor. Operable frequency range of the serial clock
is from DC to one-half the processor system clock frequency.
The serial interface operates in full-duplex mode — data is transmitted and received
simultaneously by both master and slave devices. In general, data transitions occur on
the falling edge of DSCLK and are stable by the following rising edge of DSCLK. Data
is transmitted MSB first, and is latched on the rising edge of DSCLK.
The serial data word is 17 bits wide, including 16 data bits and a status/control bit (refer
to
shows the CPU-generated message types.
CPU
SYNCHRONIZE
Figure
EXECUTION
STATUS
UNIT
3-11). Bit 16 indicates the status of CPU-generated messages.
Figure 3-10 Debug Serial I/O Block Diagram
Freescale Semiconductor, Inc.
For More Information On This Product,
PARALLEL OUT
REGISTER BUS
RCV DATA LATCH
INSTRUCTION
PARALLEL IN
SERIAL OUT
SERIAL IN
CENTRAL PROCESSOR UNIT
Go to: www.freescale.com
16
16
CONTROL
LOGIC
Rev. 25 June 03
M
DSCLK
DSO
DSI
DEVELOPMENT SYSTEM
STATUS
0
COMMAND LATCH
PARALLEL OUT
RESULT LATCH
CONTROL
PARALLEL IN
SERIAL OUT
LOGIC
SERIAL IN
DATA
DATA
16
16
MOTOROLA
32 DEBUG I/O BLOCK
Table 3-7
SERIAL
CLOCK
3-25