MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 171

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.10.3.1 Port E Data Register
PORTE0 — Port E0 Data Register
PORTE1 — Port E1 Data Register
4.10.3.2 Port E Data Direction Register
DDRAB — Port A/B Data Direction Register
DDRE — Port E Data Direction Register
4.10.3.3 Port E Pin Assignment Register
PEPAR — Port E Pin Assignment
MC68F375
REFERENCE MANUAL
MSB
15
RESET:
0
RESET:
RESET:
PEPA7
DATA8
MSB
PE7
This register can be accessed in two locations and can be read or written at any time.
A write to this register is stored in an internal data latch, and if any pin in the corre-
sponding port is configured as an output, the value stored for that bit is driven out on
the pin. A read of this data register returns the value at the pin only if the pin is config-
ured as a discrete input. Otherwise, the value read is the value stored in the register.
Bits [15:8] are reserved and will always read zero.
The port E data direction register controls the direction of the port E pin drivers when
pins are configured for I/O. Setting a bit configures the corresponding pin as an output;
clearing a bit configures the corresponding pin as an input. This register can be read
or written at any time.
The port A/B data direction register controls the direction of the pin drivers for ports A
and B, respectively, when the pins are configured for I/O. Setting DDA or DDB to one
configures all pins in the corresponding port as outputs. Clearing DDA or DDB to zero
configures all pins in the corresponding port as inputs. Bits [15:10] are reserved and
will always read zero.
This register determines the function of port E pins. Setting a bit assigns the corre-
sponding pin to a bus control signal; clearing a bit assigns the pin to I/O port E. Bits
MSB
U
7
7
14
0
13
0
PEPA6
DATA8
PE6
U
6
6
12
0
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
11
0
PEPA5
DATA8
For More Information On This Product,
PE5
U
5
5
10
0
Go to: www.freescale.com
DDA
9
PEPA4
DATA8
PE4
Rev. 25 June 03
U
4
4
DDB
8
DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0
7
0
PEPA3
DATA8
PE3
U
3
3
6
0
5
0
PEPA2
DATA8
PE2
U
2
2
4
0
3
0
PEPA1
DATA8
PE1
U
1
1
2
0
0xYF FA11
0xYF FA13
0xYF FA14
0xYF FA15
0xYF FA17
MOTOROLA
1
0
PEPA0
DATA8
LSB
PE0
LSB
U
0
0
LSB
4-89
0
0