MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 388

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
Bit(s)
2
1
0
Name
EHV
SES
PE
Program or erase select. The PE bit is write protected by the SES bit. Writes to CMFICTL will
not change PE if SES = 1. PE configures the CMFI EEPROM for programming or erasing. When
PE = 0, the array is configured for programming and if SES = 1 the SIE bit will be write locked.
When PE = 1, the array is configured for erasing and SES will not write lock the SIE bit.
0 = Configure for program operation.
1 = Configure for erase operation.
Start-end program or erase sequence. The SES bit is write protected by the HVS and EHV bits.
Writes to CMFICTL will not change SES if HVS = 1 or EHV = 1. The SES bit is used to signal
the start and end of a program or erase sequence. At the start of a program or erase sequence
SES is set (written to a 1). At this point the CMFI EEPROM is ready to receive either the pro-
gramming writes or the erase interlock write. The following bits shall be write locked: PROTECT,
BLOCK[7:0], CSC, PE. SES also write locks SCLKR[2:0], CLKPE[1:0] and CLKPM[6:0]. If PE =
0 and SES = 1, SIE will be write locked.
The erase interlock write is a write to any CMFI EEPROM array location after SES is set and PE
= 1. If the PE bit is a 0 the CMFI BIU will accept programming writes to the CMFI array address
for programming. The first programming write shall select the program page offset address
(IADDR[14|13:6]) to be programmed along with the data for the programming buffers at the loca-
tion written. All programming writes after the first shall update the program buffers using the
lower address (IADDR[5:2]) and the block address (IADDR[17|16:15|14]) to select the program
page buffers to receive the data. For further information see
After the data has been written to the program buffers the EHV bit is set (written to a 1) to start
the programming pulse and lock out further programming writes.
If the PE bit is a 1 the CMFI BIU will accept writes to the CMFI array addresses for an erase
interlock. An erase interlock write is required before the EHV bit can be set. At the end of the
program or erase operation the SES bit must be cleared (written to a 0) to return to normal oper-
ation and release the program buffers, PROTECT, SCLKR[2:0], CLKPE[1:0], CLKPM[6:0],
BLOCK[7:0], CSC and the PE bit.
0 = Not configured for program or erase operation.
1 = Configure for program or erase operation.
Enable high voltage. EHV can be asserted only after the SES bit has been asserted and a valid
programming write(s) or erase hardware interlock write has occurred. If an attempt is made to
assert EHV when SES is negated, or if a valid programming write(s) or erase hardware interlock
write has not occurred since SES was asserted, EHV will remain negated. The program or erase
enable monitor (PEEM) and EHV are used to control the application of the program or erase volt-
age to the CMFI EEPROM module. High voltage operations to the CMFI EEPROM array, special
MoneT shadow locations or FLASH NVM registers can occur only if EHV = 1 and PEEM = 1.
Only after the correct hardware and software interlocks have been applied to the CMFI
EEPROM can EHV be set. Once EHV is set SES cannot be changed and attempts to read the
array will not be acknowledged.
The default reset state of EHV disables program or erase pulses (EHV = 0). A master reset while
EHV = 1 will terminate the high voltage operation (reset CMFICTL). A system reset or setting
the STOP bit to 1 will clear EHV to a 0 terminating the high voltage pulse. The CMFI shall gen-
erate the required sequence to disable the high voltage without damage to the high voltage
circuits.
0 = Program or erase pulse disabled.
1 = Program or erase pulse enabled.
Table 10-10 CMFICTL2 Bit Settings (Continued)
Freescale Semiconductor, Inc.
CDR MoneT FLASH FOR THE IMB3 (CMFI)
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
Description
10.5.2 Program Page
MOTOROLA
Buffers.
10-18