MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 243

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
The QSMCM uses 12 pins. Eleven of the pins, when not being used by the serial sub-
systems, form a parallel port on the MCU. (The ECK pin is a dedicated external clock
source.)
The port QS pin assignment register (PQSPAR) governs the usage of QSPI pins.
Clearing a bit assigns the corresponding pin to general-purpose I/O; setting a bit
assigns the pin to the QSPI.
PQSPAR does not affect operation of the SCI. When the SCIx transmitter is disabled,
TXDx is a discrete output; when the SCIx receiver is disabled, RXDx is a discrete
input. When the SCIx transmitter or receiver is enabled, the associated TXDx or RXDx
pin is assigned its SCI function.
The port QS data direction register (DDRQS) determines whether QSPI pins are
inputs or outputs. Clearing a bit makes the corresponding pin an input; setting a bit
makes the pin an output. DDRQS affects both QSPI function and I/O function.
6-10
DDRQS does not affect SCI pin function. TXDx pins are always outputs, and RXDx
pins are always inputs, regardless of whether they are functioning as SCI pins or as
PORTQS pins.
The port QS data register (PORTQS) latches I/O data. PORTQS writes drive pins
defined as outputs. PORTQS reads return data present on the pins. To avoid driving
undefined data, write the first data to PORTQS before configuring DDRQS.
summarizes the effect of DDRQS bits on QSPI pin function.
0x30 5014
0x30 5016
0x30 5017
Address
Table 6-7 QSMCM Pin Control Registers
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
For More Information On This Product,
QSMCM Port Data Register (PORTQS)
See
descriptions.
PORTQS Pin Assignment Register (PQSPAR)
See
PORTQS Data Direction Register (DDRQS)
See
Go to: www.freescale.com
6.6.1 Port QS Data Register (PORTQS)
Table 6-11
Table 6-11
Rev. 25 June 03
for bit descriptions.
for bit descriptions.
Register
for bit
MOTOROLA
Table
6-9