MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 345

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

8.3.7 TPU3 Interrupts
8.3.8 Prescaler Control for TCR1
MC68F375
REFERENCE MANUAL
function library. Refer to the
more information about specific functions.
Each of the TPU channels can generate an interrupt service request. Interrupts for
each channel must be enabled by writing to the appropriate control bit in the channel
interrupt enable register (CIER). The channel interrupt status register (CISR) contains
one interrupt status flag per channel. Time functions set the flags. Setting a flag bit
causes the TPU to make an interrupt service request if the corresponding channel in-
terrupt enable bit is set and the interrupt request level is non-zero.
The value of the channel interrupt request level (CIRL) field in the TPU interrupt con-
figuration register (TICR) determines the priority of all TPU interrupt service requests.
CIRL values correspond to MCU interrupt request signals IRQ[7:1]. IRQ7 is the high-
est-priority request signal; IRQ1 has the lowest priority. Assigning a value of 0b111 to
CIRL causes IRQ7 to be asserted when a TPU interrupt request is made; lower field
values cause corresponding lower-priority interrupt request signals to be asserted. As-
signing CIRL a value of 0b000 disables all interrupts.
The CPU32 recognizes only interrupt requests of a priority greater than the value con-
tained in the interrupt priority (IP) mask in the status register. When the CPU32 ac-
knowledges an interrupt request, the priority of the acknowledged interrupt is written
to the IP mask and is driven out onto the IMB address lines.
When the IP mask value driven out on the address lines is the same as the CIRL value,
the TPU contends for arbitration priority. The IARB field in TPUMCR contains the TPU
arbitration number. Each module that can make an interrupt service request must be
assigned a unique non-zero IARB value in order to implement an arbitration scheme.
Arbitration is performed by means of serial assertion of IARB field bit values. The IARB
of TPUMCR is initialized to 0x0 during reset.
When the TPU wins arbitration, it must respond to the CPU32 interrupt acknowledge
cycle by placing an interrupt vector number on the data bus. The vector number is
used to calculate displacement into the exception vector table. Vectors are formed by
concatenating the 4-bit value of the CIBV field in TICR with the 4-bit number of the
channel requesting interrupt service. Since the CIBV field has a reset value of 0x0, it
must be assigned a value corresponding to the upper nibble of a block of 16 user-de-
fined vector numbers before TPU interrupts are enabled. Otherwise, a TPU interrupt
service request could cause the CPU32 to take one of the reserved vectors in the
exception vector table.
For more information about the exception vector table, refer to
tors.
Timer count register 1 (TCR1) is clocked from the output of a prescaler. The following
fields control TCR1:
Freescale Semiconductor, Inc.
For More Information On This Product,
Motorola TPU Literature Package
TIME PROCESSOR UNIT 3
Go to: www.freescale.com
Rev. 25 June 03
3.9.1 Exception Vec-
(TPULITPAK/D) for
MOTOROLA
8-5