MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 117

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.5.1.8 Data Size Acknowledge Signals
4.5.1.9 Bus Error Signal
4.5.1.10 Halt Signal
MC68F375
REFERENCE MANUAL
During normal bus transfers, external devices can assert the data size acknowledge
signals (DSACK[1:0]) to indicate port width to the MCU. During a read cycle, these sig-
nals tell the MCU to terminate the bus cycle and to latch data. During a write cycle, the
signals indicate that an external device has successfully stored data and that the cycle
can terminate. DSACK[1:0] can also be supplied internally by chip-select logic. Refer
to
The bus error signal (BERR) can be asserted by an external source when a bus cycle
is not properly terminated by DSACK or AVEC assertion. It can also be asserted in
conjunction with DSACK to indicate a bus error condition, provided it meets the appro-
priate timing requirements. Refer to
information.
The internal bus monitor can generate the BERR signal for excessively long internal-
to-external transfers. In systems with an external bus master, the SCIM2E bus monitor
must be disabled and external logic must be provided to drive the BERR pin, because
the internal BERR monitor has no information about transfers initiated by an external
bus master. Refer to
The halt signal (HALT) can be asserted by an external device for debugging purposes
to cause single bus cycle operation or (in combination with BERR) a retry of a bus
cycle in error. The HALT signal affects external bus cycles only. As a result, a program
not requiring use of the external bus may continue executing, unaffected by the HALT
signal. When the MCU completes a bus cycle with the HALT signal asserted,
DATA[15:0] is placed in a high-impedance state and AS and DS are driven inactive;
the address, function code, size, and read/write signals remain in the same state. The
MCU does not service interrupt requests while it is halted. Refer to
tion Control Cycles
4.9 Chip Selects
FC2
0
0
0
0
1
1
1
1
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
for more information.
4.6.6 External Bus Arbitration
Table 4-18 Address Space Encoding
for further information.
For More Information On This Product,
FC1
0
0
1
1
0
0
1
1
Go to: www.freescale.com
Rev. 25 June 03
4.6.5 Bus Exception Control Cycles
FC0
0
1
0
1
0
1
0
1
Reserved
User data space
User program space
Reserved
Reserved
Supervisor data space
Supervisor Program space
CPU space
for more information.
Address Space
4.6.5 Bus Excep-
MOTOROLA
for more
4-35