MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 997

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
0xDB4–
0xDD4–
0xC74–
0xC94–
0xDF4–
0xDBC
0xDCC
0xDDC
0xDEC
0xC7C
0xC8C
0xD9C
0xDAC
0xDC0
0xDC4
0xDC8
0xDD0
0xDFC
Offset
0xC80
0xC84
0xC88
0xC90
0xDA0
0xDA4
0xDA8
0xDB0
0xDE0
0xDE4
0xDE8
0xDF0
0xE00
0xE04
0xE08
Reserved
POTAR4—PCI outbound window 4 translation address register
POTEAR4—PCI outbound window 4 translation extended address
register
POWBAR4—PCI outbound window 4 base address register
Reserved
POWAR4—PCI outbound window 4 attributes register
Reserved
PITAR3—PCI inbound window 3 translation address register
Reserved
PIWBAR3—PCI inbound window 3 base address register
PIWBEAR3—PCI inbound window 3 base extended address register
PIWAR3—PCI inbound window 3 attributes register
Reserved
PITAR2—PCI inbound window 2 translation address register
Reserved
PIWBAR2—PCI inbound window 2 base address register
PIWBEAR2—PCI inbound window 2 base extended address register
PIWAR2—PCI inbound window 2 attributes register
Reserved
PITAR1—PCI inbound window 1 translation address register
Reserved
PIWBAR1—PCI inbound window 1 base address register
Reserved
PIWAR1—PCI inbound window 1 attributes register
Reserved
ERR_DR—PCI error detect register
ERR_CAP_DR—PCI error capture disabled register
ERR_EN—PCI error enable register
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 17-3. PCI Memory-Mapped Register Map (continued)
Register
0xC80–0xC9C—Outbound Window 4
0xDC0–0xDDC–Inbound Window 2
0xDA0–0xDBC–Inbound Window 3
0xDE0–0xDFC–Inbound Window 1
PCI Error Management Registers
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
w1c
—
—
—
—
—
—
—
—
—
—
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
—
—
—
—
—
—
—
—
—
—
17.3.1.2.1/17-16
17.3.1.2.2/17-16
17.3.1.2.3/17-17
17.3.1.2.4/17-18
17.3.1.3.1/17-20
17.3.1.3.2/17-20
17.3.1.3.3/17-21
17.3.1.3.4/17-21
17.3.1.3.1/17-20
17.3.1.3.2/17-20
17.3.1.3.3/17-21
17.3.1.3.4/17-21
17.3.1.3.1/17-20
17.3.1.3.2/17-20
17.3.1.3.4/17-21
17.3.1.4.1/17-24
17.3.1.4.2/17-25
17.3.1.4.3/17-26
PCI Bus Interface
Section/page
17-13