MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 781

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.5.3.2.11 Transmit Descriptor Base Address Registers (TBASE0–TBASE7)
The TBASEn registers are written by the user with the base address of each TxBD ring n. Each such value
must be divisible by eight, since the three least significant bits always write as 000.
the definition for the TBASEn registers.
Table 15-25
15.5.3.3
This section describes the control and status registers that are used specifically for receiving Ethernet
frames. All of the registers are 32 bits wide.
15.5.3.3.1
The RCTRL register is programmed by the user and controls the operational mode of the receiver. It must
be written only after a system reset (at initialization) or after a graceful receive stop has completed.
Figure 15-22
Offset eTSEC1:0x2_4300; eTSEC3:0x2_5300
Freescale Semiconductor
Reset
Reset
29–31
0–28 TBASE n Transmit base for ring n . TBASE defines the starting location in the memory map for the eTSEC TxBDs. This
Bits
Offset eTSEC1:0x2_4204+8× n ; eTSEC3:0x2_5204+8× n
Reset
W
W
R
R
W
R
—
16
Name
0
—
0
LFC VLEX FILREN FSQEN GHTX IPCSEN TUCSEN
describes the fields of the TBASEn registers.
17
eTSEC Receive Control and Status Registers
describes the RCTRL register.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
field must be 8-byte aligned. Together with setting the W (wrap) bit in the last BD, the user can select how many
BDs to allocate for the transmit packets. The user must initialize TBASE before enabling the eTSEC transmit
function on the associated ring.
Reserved
Receive Control Register (RCTRL)
18
19
Table 15-25. TBASE0–TBASE7 Field Descriptions
Figure 15-22. RCTRL Register Definition
Figure 15-21. TBASE Register Definition
20
—
21
22
TBASE n
All zeros
All zeros
All zeros
Description
23
24
PRSDEP
25
Enhanced Three-Speed Ethernet Controllers
10
— BC_REJ PROM RSF EMEN —
26
11
27
Figure 15-21
28
Access: Read/Write
Access: Read/Write
PAL
29
28 29
describes
30
—
15-49
31
15
31