MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 159

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 4
Reset, Clocking, and Initialization
This chapter describes the reset, clocking, and some overall initialization of the MPC8544E, including a
definition of the reset configuration signals and the options they select. Additionally, the configuration,
control, and status registers are described. Note that other chapters in this book may describe specific
aspects of initialization for individual blocks.
4.1
The reset, clocking, and control signals provide many options for the operation of the MPC8544E.
Additionally, many modes are selected with reset configuration signals during a hard reset (assertion of
HRESET).
4.2
Table 4-1
signal descriptions, but
The following sections describe the reset and clock signals in detail.
Freescale Semiconductor
SD2_REF_CLK/
SD2_REF_CLK
HRESET_REQ
SD_REF_CLK/
SD_REF_CLK
HRESET
SRESET
SYSCLK
READY
Signal
RTC
Overview
External Signal Descriptions
summarizes the external signals described in this chapter.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
I/O
O Hard reset request output. An internal block requests that HRESET be asserted.
O The MPC8544E has completed the reset operation and is not in a power-down
I
I
I
I
I
I
Hard reset input. Causes a power-on reset (POR) sequence.
Soft reset input. Causes mcp assertion to the core
(nap, doze or sleep) or debug state.
Primary clock input to the MPC8544E
Real time clock input
SERDES high-speed interface reference clock
Second SERDES high-speed interface reference clock
Table 4-1
contains references to additional sections that contain more information.
Table 4-1. Signal Summary
Description
Table 4-2
and
Table 4-3
(Section/Page)
have detailed
References
4.4.4.1/4-23
4.4.4.4/4-25
4.4.4.2/4-24
4.4.4.2/4-24
4.4.1.2/4-8
4.4.1.1/4-8
4.4.2/4-9
—
4-1