MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1306

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Complete List of Configuration, Control, and Status Registers
1
2
3
4
5
6
B-40
Implementation-dependent reset values are listed in specified section/page.
I
0x100 to 0x114.
Port size for BR0 is configured from external signals during reset, hence ‘ nn ’ is either 0x08, 0x10, or 0x18.
Registers denoted * are new to the enhanced TSEC and not supported by PowerQUICC III TSECs.
Cleared on read.
eTSEC3 has the same memory-mapped registers that are described for eTSEC1 from 0x 2_4000 to 0x2_4FFF, except the
offsets are from 0x 2_5000 to 0x2_5FFF.
0xE_204C
0xE_205C
0xE_20A0
0xE_20A4
0xE_2040
0xE_2044
0xE_2054
0xE_2058
0xE_2060
0xE_2064
0xE_2068
2
C2 has the same memory-mapped registers that are described for I
Offset
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
TBCR0—Trace buffer control register 0
TBCR1—Trace buffer control register 1
TBAR—Trace buffer address register
TBAMR—Trace buffer address mask register
TBTMR—Trace buffer transaction mask register
TBSR—Trace buffer status register
TBACR—Trace buffer access control register
TBADHR—Trace buffer access data high register
TBADR—Trace buffer access data register
PCIDR—Programmed context ID register
CCIDR—Current context ID register
Table B-1. Memory Map (continued)
Register
Trace Buffer Registers
Context ID Registers
2
C1 from 0x000 to 0x014, except the offsets range from
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
Freescale Semiconductor
21.3.2.1/21-16
21.3.2.1/21-16
21.3.2.2/21-19
21.3.2.3/21-19
21.3.2.4/21-20
21.3.2.5/21-20
21.3.2.6/21-21
21.3.2.7/21-22
21.3.2.8/21-22
21.3.3.1/21-23
21.3.3.2/21-24
Section/Page