MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 712

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Local Bus Controller
Clock low-to-high transitions
CKE
Supplier specific
minimum time
COMMAND
NOP
NOP
NOP
(As defined by
S, RE, CE, W,
New command
and ADDR)
accepted here
All banks idle
Cannot violate minimum
refresh specification
Figure 14-75. SDRAM Power-Down Timing
CKE remains low, as long as the device is powered down. After CKE transitions to high, the SDRAM exits
the power-down mode.
14.5.4.3.7
Self-Refresh
In order to be able to stop activity on the local bus (for power save or debug), while the content of the
SDRAM is maintained, the self-refresh mode is supported. This mode is invoked by issuing a self-refresh
command to the SDRAM. The LBC applies the same timing as for the auto refresh, but also pulls the
SDRAM CKE (LCKE) signal low in the same cycle. This can only be done with all banks being idle; the
SDRAM machine must precharge them ahead of this. As long as CKE stays low, the device refreshes itself
and does not need to see any refreshes from the local bus. To exit self refresh, CKE simply has to be pulled
high. Note that after returning from self-refresh mode the SDRAM needs a supplier-specific time before
it can accept new commands and the auto-refresh mechanism has to be started again.
Figure 14-76
shows
this timing. The SDRAM controller always uses 200 local bus clocks, which should satisfy any SDRAM
requirements. As in the case of the power-down mode, the figure does not show the precharge-all
command that is issued by the LBC automatically prior to the self-refresh command.
1. Refer to
Section 14.4.3.3, “Intel PC133 and JEDEC-Standard SDRAM Interface Commands,”
for
SDRAM interface commands and information on the self-refresh command.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
14-92
Freescale Semiconductor