MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 918

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
15-186
Set up the MII Mgmt for a write cycle to the external PHY Mode control register to set up the interface mode selection,
Other information about the link is also returned.(Extend Status, No pre, Remote Fault, An Ability, Link status, extend
Set up the MII Mgmt for a write cycle to the external PHY Extended PHY control register #1 to set up the interface
Set up the MII Mgmt for a read cycle to PHY MII Mgmt register (write the PHY address and Register address),
If auto-negotiation was enabled in the PHY, check to see if PHY has completed Auto-Negotiation.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
The PHY Status register is at address 0x1 and in this case the PHY Address is 0x00
(Uses the PHY address (0) and Register address (1) placed in MIIMADD register),
Write to MII Mgmt Control with 16-bit data intended for the external PHY register,
Write to MII Mgmt Control with 16-bit data intended for the external PHY register,
Table 15-153. GMII Mode Register Initialization Steps (continued)
Read the MIIMSTAT register and check bit 10 (AN Done and Link is up),
MACnADDR1/2[0000_0000_0000_0000_0000_0000_0000_0000]
MIIMSTAT ---> [0000_0000_0000_0000_0000_0000_0010_0100]
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
MIIMCON[0000_0000_0000_0000_0000_0000_0000_0000]
MIIMCON[0000_0000_0000_0000_000u_00u1_0100_0000]
MIIMADD[0000_0000_0000_0000_0000_0000_0001_0111]
MIIMADD[0000_0000_0000_0000_0000_0000_0000_0000]
MIIMADD[0000_0000_0000_0000_0000_0000_0000_0001]
GADDR n [0000_0000_0000_0000_0000_0000_0000_0000]
Check auto-negotiation attributes in the PHY as necessary.
IEVENT[0000_0000_0000_0000_0000_0000_0000_0000]
RCTRL[0000_0000_0000_0000_0000_0000_0000_0000]
IMASK[0000_0000_0000_0000_0000_0000_0000_0000]
Read MII Mgmt Indicator register and check for Busy = 0,
Read MII Mgmt Indicator register and check for Busy = 0,
Read MII Mgmt Indicator register and check for Busy = 0,
where u is user defined based on desired configuration.
Perform an MII Mgmt write cycle to the external PHY.
Perform an MII Mgmt write cycle to the external PHY.
Perform an MII Mgmt read cycle of Status Register.
This indicates that the write cycle was completed.
This indicates that the write cycle was completed.
This indicates that the write cycle was completed
Check to see if MII Mgmt write is complete.
Check to see if MII Mgmt write is complete.
Check to see if MII Mgmt write is complete.
Initialize MACnADDR1/2 (Optional)
Clear MIIMCOM[Read Cycle].
Initialize GADDR n (Optional)
Set MIIMCOM[Read Cycle].
Initialize RCTRL (Optional)
When MIIMIND[BUSY]=0,
Initialize IMASK (Optional)
Clear IEVENT register,
mode selection
Ability)
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