MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1199

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

19.5.1.9
When the MPC8544E is in doze mode, the e500 core is in the core-halted state and it snoops its L1 caches
and full coherency is maintained. In deeper power-down modes, however, the e500 core does not respond
to snoops.
The MPC8544E does not perform dynamic bus snooping as described in the e500 Reference Manual. That
is, when the e500 core is in the core-stopped state (which is the state of the core when the MPC8544E is
in either the nap or sleep state), the core is not awakened to perform snoops on global transactions.
Therefore, before entering nap or sleep modes, the L1 caches should be flushed if coherency is required
during these power-down modes.
19.5.1.10 Software Considerations for Power Management
Setting MSR[WE] generates a request to the MPC8544E logic (external to the core complex) to enter a
power saving state. It is assumed that the desired power-saving state (doze, nap, or sleep) was set up by
setting the appropriate HID0 bit, typically at system start-up time. Setting WE has no direct effect on
instruction execution, but is reflected on the internal doze, nap, and sleep signals, depending on the HID0
settings. To ensure a clean transition into and out of a power-saving mode, the following program sequence
is recommended:
19.5.1.11 Requirements for Reaching and Recovering from Sleep State
In order to successfully reach the sleep state, I/O traffic to the device must be stopped. The logic that
controls the power down sequence waits for all I/O interfaces to become idle. In some applications this
may happen eventually without actively shutting down interfaces, but most likely, software will have to
take steps to shut down the eTSEC, and PCI interfaces before issuing the command (either the write to the
core MSR[WE] as described above or writing to POWMGTCSR) to put the device into sleep state.
The PCI interfaces will begin retrying inbound transactions before entering a power down state. The PCI
interfaces, however, could potentially be in an unknown state when they exit sleep if they were in the
middle of a retry sequence when internal clocks were shut down. Therefore it is strongly recommended
that system software clear the memory space bit in the PCI Bus Command Register before putting the
device in sleep mode. Software may also need to set the Agent Config Lock bit of the PCI Bus Function
Register so that the device will not respond to configuration transactions. Upon exiting sleep mode,
software should return these configuration bits to their normal state.
Freescale Semiconductor
Snooping in Power-Down Modes
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
loop:
sync
mtmsr (WE)
isync
br loop
Global Utilities
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