MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1293

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
0x3_6100–0x3
0x3_6400–0x3
0x3_6800–0x3
0x3_8100–0x3
0x3_8800–0x3
0x3_6038
0x3_6040
0x3_6050
0x3_8000
0x3_8010
0x3_8018
0x3_8028
0x3_8030
0x3_8038
0x3_8050
0x3_8200
0x3_8400
0x3_8480
0x3_A000
(3_8E00)
0x3_808
_6FFF
_8FFF
_647F
_81FF
_6120
Offset
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
MDEUICR—MDEU interrupt control register
MDEUICVSR—MDEU ICV size register
MDEUEUG—MDEU EU go register
MDEU context memory registers
MDEU key memory
MDEU FIFO
AFEUMR—AFEU mode register
AFEUKSR—AFEU key size register
AFEUDSR—AFEU data size register
AFEURCR—AFEU reset control register
AFEUSR—AFEU status register
AFEUISR—AFEU interrupt status register
AFEUICR—AFEU interrupt control register
AFEUEUG—AFEU EU go register
AFEU context memory registers
AFEU context memory pointers
AFEUK1—AFEU key register 0
AFEUK2—AFEU key register 1
AFEU FIFO
RNGMR—RNG mode register
Table B-1. Memory Map (continued)
Register
Random Number Generator (RNG)
ARC Four Execution Unit (AFEU)
Complete List of Configuration, Control, and Status Registers
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
W
W
W
W
W
R
R
0x0000_0000_
0x0000_0000_
0x0000_0000_
0x0000_0000_
0x0000_0000_
0x0000_0000_
0x0000_0000_
0x0000_0000_
0x0000_0000_
0x0000_0000_
0x0000_0000_
0x0000_0000_
0x0000_0000_
0x0000_0000_
0x0000_0000_
0x0000_0000_
0x0000_0000_
0x0000_0000_
0000_1000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_1000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
Reset
—
—
12.4.3.10.1/12-49
12.4.3.10.2/12-50
12.4.4.10/12-59
12.4.4.11/12-60
12.4.4.12/12-61
12.4.4.13/12-62
12.4.3.11/12-50
12.4.3.11/12-50
12.4.3.12/12-50
12.4.4.8/12-58
12.4.4.9/12-59
12.4.3.1/12-42
12.4.3.3/12-43
12.4.3.4/12-44
12.4.3.5/12-44
12.4.3.6/12-45
12.4.3.7/12-46
12.4.3.8/12-48
12.4.3.9/12-49
12.4.5.1/12-63
Section/Page
B-27