MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 23

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Paragraph
Number
13.3.1.2
13.3.1.3
13.3.1.4
13.3.1.5
13.3.1.6
13.3.1.7
13.3.1.8
13.3.1.9
13.3.1.10
13.3.1.11
13.3.1.12
13.3.1.13
13.4
13.4.1
13.4.1.1
13.4.1.2
13.4.1.3
13.4.1.4
13.4.2
13.4.3
13.4.4
13.4.4.1
13.4.4.2
13.4.4.3
13.4.5
13.4.5.1
13.4.5.2
13.4.5.3
13.5
14.1
14.1.1
14.1.2
14.1.3
14.1.3.1
14.1.3.2
14.1.4
Freescale Semiconductor
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Functional Description................................................................................................. 13-19
DUART Initialization/Application Information .......................................................... 13-24
Introduction.................................................................................................................... 14-1
Serial Interface......................................................................................................... 13-20
Baud-Rate Generator Logic ..................................................................................... 13-21
Local Loopback Mode ............................................................................................. 13-22
Errors ....................................................................................................................... 13-22
FIFO Mode .............................................................................................................. 13-22
Overview.................................................................................................................... 14-2
Features...................................................................................................................... 14-2
Modes of Operation ................................................................................................... 14-3
Power-Down Mode.................................................................................................... 14-4
Transmitter Holding Registers (UTHR0, UTHR1) (ULCR[DLAB] = 0) ............. 13-6
Divisor Most and Least Significant Byte Registers (UDMB and UDLB)
Interrupt Enable Register (UIER) (ULCR[DLAB] = 0)........................................ 13-9
Interrupt ID Registers (UIIR0, UIIR1) (ULCR[DLAB] = 0) ................................ 13-9
FIFO Control Registers (UFCR0, UFCR1) (ULCR[DLAB] = 0)....................... 13-11
Line Control Registers (ULCR0, ULCR1).......................................................... 13-12
Modem Control Registers (UMCR0, UMCR1)................................................... 13-14
Line Status Registers (ULSR0, ULSR1) ............................................................. 13-15
Modem Status Registers (UMSR0, UMSR1) ...................................................... 13-16
Scratch Registers (USCR0, USCR1) ................................................................... 13-17
Alternate Function Registers (UAFR0, UAFR1) (ULCR[DLAB] = 1) .............. 13-17
DMA Status Registers (UDSR0, UDSR1) .......................................................... 13-18
START Bit ........................................................................................................... 13-20
Data Transfer ....................................................................................................... 13-21
Parity Bit .............................................................................................................. 13-21
STOP Bit.............................................................................................................. 13-21
Framing Error ...................................................................................................... 13-22
Parity Error .......................................................................................................... 13-22
Overrun Error....................................................................................................... 13-22
FIFO Interrupts .................................................................................................... 13-23
DMA Mode Select ............................................................................................... 13-23
Interrupt Control Logic........................................................................................ 13-23
LBC Bus Clock and Clock Ratios ......................................................................... 14-3
Source ID Debug Mode ......................................................................................... 14-4
(ULCR[DLAB] = 1) .......................................................................................... 13-7
Local Bus Controller
Contents
Chapter 14
Title
Number
Page
xxiii