MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 8

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Paragraph
Number
4.4.3.18
4.4.3.19
4.4.3.20
4.4.3.21
4.4.3.22
4.4.4
4.4.4.1
4.4.4.2
4.4.4.2.1
4.4.4.3
4.4.4.4
5.1
5.1.1
5.1.2
5.2
5.3
5.3.1
5.4
5.5
5.5.1
5.5.2
5.5.3
5.6
5.7
5.8
5.8.1
5.8.2
5.8.3
5.8.4
5.8.5
5.9
5.9.1
5.9.2
5.9.3
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MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Overview.......................................................................................................................... 5-1
e500 Processor and System Version Numbers................................................................. 5-4
Features ............................................................................................................................ 5-5
Instruction Set ................................................................................................................ 5-11
Instruction Flow ............................................................................................................. 5-13
Programming Model ...................................................................................................... 5-16
On-Chip Cache Implementation .................................................................................... 5-18
Interrupts and Exception Handling ................................................................................ 5-18
Memory Management.................................................................................................... 5-22
Clocking..................................................................................................................... 4-23
Upward Compatibility ................................................................................................. 5-3
Core Complex Summary ............................................................................................. 5-3
e500v2 Differences .................................................................................................... 5-10
Initial Instruction Fetch.............................................................................................. 5-13
Branch Detection and Prediction ............................................................................... 5-13
e500 Execution Pipeline ............................................................................................ 5-14
Exception Handling ................................................................................................... 5-18
Interrupt Classes ........................................................................................................ 5-19
Interrupt Types ........................................................................................................... 5-19
Upper Bound on Interrupt Latencies ......................................................................... 5-20
Interrupt Registers...................................................................................................... 5-20
Address Translation ................................................................................................... 5-24
MMU Assist Registers (MAS0–MAS4 and MAS6–MAS7)..................................... 5-25
Process ID Registers (PID0–PID2)............................................................................ 5-26
PCI I/O Impedance ................................................................................................ 4-21
PCI Arbiter Configuration ..................................................................................... 4-22
Memory Debug Configuration .............................................................................. 4-22
DDR Debug Configuration.................................................................................... 4-22
General-Purpose POR Configuration .................................................................... 4-23
System Clock/PCI Clock ....................................................................................... 4-23
PCI Express and SGMII Clocks ............................................................................ 4-24
Ethernet Clocks...................................................................................................... 4-25
Real Time Clock .................................................................................................... 4-25
Minimum Frequency Requirements .................................................................. 4-24
e500 Core Complex and L2 Cache
Core Complex Overview
Contents
Chapter 5
Part II
Title
Freescale Semiconductor
Number
Page