MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 433

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.3.5.2
The MER shown in
be set to enable interrupt generation when the corresponding message register is written.
When bits in MER are set to mask message interrupts, an interrupt is not generated if the message register
is written while it is masked in MER and the MER bit is then cleared. To mask the interrupt without loss,
set MIVPRn[MSK]. (See
(MIVPR0–MIVPR3).”) MER should be set to 0x0000_000F at reset and be left unchanged during normal
operation.
Table 10-33
10.3.5.3
The PIC message status register (MSR) shown in
register. The status bit is set when the corresponding messaging interrupt is active. Writing a one to a status
bit clears the corresponding message interrupt and the status bit.
Freescale Semiconductor
Offset 0x4_1500
Reset
28–31
0–27
Bits
Offset 0x4_1510
Reset
W
R
W
R
0
E3–E0 Enable n . Used to enable interrupt generation for MSGR n .
Name
0
—
describes the MER fields.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Message Enable Register (MER)
Message Status Register (MSR)
Reserved
0 Interrupt generation for MSGR n disabled.
1 Interrupt generation for MSGR n enabled.
Figure 10-29
Section 10.3.7.5, “Messaging Interrupt Vector/Priority Registers
Figure 10-29. Message Enable Register (MER)
Figure 10-30. Message Status Register (MSR)
contains the enable bits for each message register. The enable bit must
Table 10-33. MER Field Descriptions
—
—
Figure 10-30
All zeros
All zeros
Description
contains status bits for each message
Programmable Interrupt Controller
Access: Read/Write
Access: Read/Write
27 28 29 30 31
27 28 29 30 31
S3 S2 S1 S0
E3 E2 E1 E0
10-35