MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1110

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PCI Express Interface Controller
18.3.8.2.8
This register does not apply to PCI Express. It is present for legacy purposes.
18.3.8.3
The type 1 header is shown in
Section 18.3.8.1, “Common PCI Compatible Configuration Header
the first 16 bytes of the header. This section describes the registers that are unique to the type 1 header
beginning at offset 0x10.
18-56
Offset 0x3F (EP-mode only)
Reset
Bits
W
7–0
Reserved
R
Secondary Latency Timer
MAX_LAT Does not apply for PCI Express.
7
Name
BIST
Type 1 Configuration Header
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
PCI Express Maximum Latency Register (EP-Mode Only)—0x3F
Prefetchable Memory Limit
Figure 18-58. PCI Express PCI-Compatible Configuration Header—Type 1
I/O Limit Upper 16 Bits
Table 18-54. PCI Express Maximum Latency Register Field Description
Secondary Status
Figure 18-57. PCI Express Maximum Latency Register (MAX_LAT)
Bridge Control
Memory Limit
Device ID
Status
Subordinate Bus Number
Figure
Header Type
Class Code
Prefetchable Base Upper 32 Bits
Prefetchable Limit Upper 32 Bits
18-58.
Base Address Register 0
MAX_LAT
All zeros
Secondary Bus Number
Latency Timer
Description
Interrupt Pin
I/O Limit
Prefetchable Memory Base
I/O Base Upper 16 Bits
Registers,” describes the registers in
Memory Base
Command
Vendor ID
Primary Bus Number
Capabilities Pointer
Cache Line Size
Interrupt Line
Revision ID
I/O Base
Freescale Semiconductor
Access: Read-only
Offset (Hex)
Address
0
00
04
08
0C
10
14
18
1C
20
24
28
2C
30
34
3C