MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 157

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.3
When a system reset is recognized (HRESET is asserted), the MPC8544E aborts all current internal and
external transactions and releases all bidirectional I/O signals to a high-impedance state. See
“Reset, Clocking, and Initialization,”
During reset, the MPC8544E ignores most input signals (except for the reset configuration signals) and
drives most of the output-only signals to an inactive state.
Freescale Semiconductor
Output Signal States During Reset
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
DDR Memory
DDR Memory
DDR Memory
DDR Memory
DDR Memory
DDR Memory
DDR Memory
DDR Memory
DDR Memory
PCI Express
PCI Express
Interface
TSEC1
TSEC1
TSEC1
TSEC3
TSEC3
TSEC3
TSEC3
TSEC3
Analog
DMA
DMA
LBC
LBC
LBC
LBC
Table 3-4. Output Signal States During System Reset
MBA[2:0]
MA[15:0]
MWE
MRAS
MCAS
MCS[0:3]
MCKE[0:3]
MCK[0:5], MCK[0:5]
MODT[0:3]
SD_TX[7:0], SD_TX[7:0]
SD_PLL_TPD
SD_PLL_TPA
TSEC1_TX_EN
TSEC1_TX_ER
TSEC1_GTX_CLK
TSEC3_TX_EN
TSEC3_GTX_CLK
TSEC3_TXD[3]
TSEC3_TXD[6:7]
TSEC3_TX_ER
LCLK[0:2]
LCKE
LCS[0:4]
DMA_DACK2/LCS6
DMA_DDONE2/LCS7
DMA_DACK[0:1]
DMA_DACK2/LCS6
DMA_DDONE2/LCS7
for a complete description of the reset functionality.
Signal
Input—reset config (test only)
Input—reset config (test only)
State During Reset
Input—reset config
Driven Toggling
Driven Low
Driven Low
Driven
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Driven
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
1
2
2
Signal Descriptions
Chapter 4,
3-17