MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 809

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.5.3.5.12 Interface Status Register (IFSTAT)
Figure 15-47
Table 15-50
15.5.3.5.13 MAC Station Address Part 1 Register (MACSTNADDR1)
The MACSTNADDR1 register is written by the user. The value of the station address written into
MACSTNADDR1 and MACSTNADDR2 is byte reversed from how it would appear in the DA field of a
frame in memory. For example, for a station address of 0x12345678ABCD, MACSTNADDR1 is set to
0xCDAB7856 and MACSTNADDR2 is set to 0x34120000.
Freescale Semiconductor
Offset eTSEC1:0x2_453C; eTSEC3:0x2_553C
Reset
23–31
0–21
Bits
22
W
R
0
0–28
Bits
29
30
31
Excess Defer Excessive transmission defer. This bit latches high and is cleared when read. This bit is cleared by
Name
describes the fields of the FSTAT register.
shows the IFSTAT register.
—
—
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Not Valid Not valid.
Name
Scan
Busy
—
Reserved
default.
0 Normal operation.
1 The MAC excessively defers a transmission.
Reserved
Reserved
0 MII Mgmt read cycle has completed and the read data is valid.
1 MII Mgmt read cycle has not completed and the read data is not yet valid.
Scan in progress.
0 A scan operation (continuous MII Mgmt read cycles) is not in progress.
1 A scan operation (continuous MII Mgmt read cycles) is in progress.
Busy.
0 MII Mgmt block is not currently performing an MII Mgmt read or write cycle.
1 MII Mgmt block is currently performing an MII Mgmt read or write cycle.
Figure 15-47. Interface Status Register Definition
Table 15-49. MIIMIND Field Descriptions
Table 15-50. IFSTAT Field Descriptions
—
All zeros
Description
Description
21
Excess Defer
Enhanced Three-Speed Ethernet Controllers
22
23
Access: Read only
—
15-77
31