MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1017

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
Offset 0x06
Reset
Reset
.
10–9
Bits
3–0
W
W
15
14
13
12
11
R
R Fast back-to-
8
7
6
5
4
back capable
parity error
Master data parity
Detected
Fast back-to-back
Signaled system
66-MHz capable Read-only bit indicates that this PCI controller is capable of 66 MHz PCI bus operation.
DEVSEL timing
Capabilities List Hard-wired to 0
Detected parity
error detected
w1c
master-abort
target-abort
target-abort
15
7
1
Received
Received
Signaled
capable
Name
error
error
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
—
—
system error
Signaled
w1c
—
14
0
6
Set whenever this PCI controller detects a PCI parity error, even if parity error handling is
disabled (as controlled by bit 6 in the PCI bus command register).
Set whenever this PCI controller asserts PCI_SERR.
Set whenever this PCI controller, acting as the PCI master, terminates a transaction (except for
a special-cycle) using master-abort.
Set whenever a PCI transaction initiated by this PCI controller (excluding a special-cycle) is
terminated by a target-abort.
Set whenever this PCI controller, acting as the PCI target, issues a target-abort to a PCI master.
Hard-wired to 0b00, indicating that this PCI controller uses fast device select timing.
Set upon detecting a data parity error. Three conditions must be met for this bit to be set:
Hard-wired to 1, indicating that this PCI controller (as a target) is capable of accepting fast
back-to-back transactions.
Reserved
Reserved
• This PCI controller detected a parity error.
• This PCI controller was acting as the bus master for the operation in which the error occurred.
• Bit 6 in the PCI bus command register was set.
Table 17-27. PCI Bus Status Register Field Descriptions
master-abort
Received
66-MHz
capable
Figure 17-28. PCI Bus Status Register
w1c
13
1
5
target-abort
Capabilities
Received
w1c
list
12
0
4
All zeros
target-abort
Signaled
w1c
Description
11
0
3
10
DEVSEL timing
0
—
9
0
Master data parity
PCI Bus Interface
error detected
Access: Mixed
w1c
8
0
0
17-33