MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1175

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
10–12
17–19
20–21
22–24
25–26
27–31
Bits
13
14
15
16
PCI_ARB
PCI_SPD
IO_SEL
RTYPE
Name
ECP3
—
—
—
—
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
I/O port selection mode (See
000 All PCI Express ports powered down, SGMII ports powered down
001 All PCI Express ports powered down, SGMII ports active
010 PCI Express port 1 active, PCI Express port 2 and 3 powered down, SGMII ports powered down
011 PCI Express port 1 active, PCI Express port 2 and 3 powered down, SGMII ports active
100 PCI Express port 1 and 2 active, PCI Express port 3 powered down, SGMII ports powered down
101 PCI Express port 1 and 2 active, PCI Express port 3 powered down, SGMII ports active
110 All PCI Express active, SGMII ports powered down
111 All PCI Express active, SGMII ports active
PCI Express 1:
RX lane[0:3] -> SD1_RX[0:3]
TX lane [0:3] -> SD1_TX[0:3]
PCI Express 2:
RX lane[0:3] -> SD1_RX[4:7]
TX lane [0:3] -> SD1_TX[4:7]
PCI Express 3:
RX lane[0] -> SD2_RX[0]
TX lane [0] -> SD2_TX[0]
SGMII:
RX lane[0:1] -> SD2_RX[2:3]
TX lane [0:1] -> SD2_TX[2:3]
Reserved
PCI arbiter enable (See
0 PCI arbiter is disabled
1 PCI arbiter is enabled
Reserved
PCI speed (See
0 PCI set for low speed operation—PCI below 33MHz
1 PCI set for normal speed operation—PCI at or above 33MHz
Reserved
eTSEC3 controller protocol (See
00 The eTSEC3 controller operates using the 8-bit FIFO protocol.
01 The eTSEC3 controller operates using the MII protocol (or RMII if configured in reduced mode).
10 The eTSEC3 controller operates using the GMII protocol (or RGMII if configured in reduced mode).
11 The eTSEC3 controller operates using the TBI protocol (or RTBI if configured in reduced mode).
Reserved
DRAM Type (See
00 Low power DDR I
01 DDR I or FCRAM I (or 60x or 8539)
10 Reserved
11 DDR II, FCRAM I, FCRAM II
Reserved
Table 19-7. PORDEVSR Field Descriptions (continued)
Section 4.4.3.17, “PCI Speed
Section 4.4.3.9, “DDR SDRAM
Section 4.4.3.19, “PCI Arbiter
Section 4.4.3.6, “I/O Port
Section 4.4.3.14, “eTSEC3
Description
Configuration.”)
Type.”)
Configuration.”)
Selection.”)
Protocol.”)
Global Utilities
19-9