MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 242

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Core Register Summary
6.9.3
6-24
Reset
32–53
58–62
SPR 1013
Bits
54
55
56
57
63
W
R
32
BBLFC Branch buffer lock bits flash clear. Clearing and then setting BBLFC flash clears the lock bit of all entries in
Name
BBLO Branch buffer lock overflow status
BPEN Branch prediction enable
BBUL Branch buffer unable to lock
BBFI
—
—
Branch Unit Control and Status Register (BUCSR)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved, should be cleared.
Branch buffer flash invalidate. Clearing and then setting BBFI flash clears the valid bit of all entries in the
branch buffer; clearing occurs independently from the value of the enable bit (BPEN). BBFI is always read as
0.
0 Indicates a lock overflow condition was not encountered in the branch buffer
1 Indicates a lock overflow condition was encountered in the branch buffer
This sticky bit is set by hardware and is cleared by writing 0 to this bit location.
0 Indicates a lock overflow condition in the branch buffer
1 Indicates a lock set instruction failed in the branch buffer, for example, if the BTB is disabled.
This sticky bit is set by hardware and is cleared by writing 0 to this bit location.
the branch buffer; clearing occurs independently from the value of the enable bit (BPEN). BBLFC is always
read as 0.
Reserved, should be cleared.
0 Branch prediction disabled
1 Branch prediction enabled (enables BTB to predict branches)
Figure 6-31. Branch Unit Control and Status Register (BUCSR)
—
Table 6-17. BUCSR Field Descriptions
All zeros
Description
53
BBFI BBLO BBUL BBLFC
54
55
56
Access: Supervisor read/write
57
Freescale Semiconductor
58
—
62
BPEN
63