MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 851

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.5.4.3.3
Figure 15-109
Table 15-113
Freescale Semiconductor
Bits
Bits
10
11
12
13
14
15
0
1
Offset 0x04
Reset
W
R
Remote
Extend
Status
Name
Name
Ability
Ability
Page
Done
Fault
Next
Link
Page
AN
AN
Next
—
—
0
describes the fields of the ANA register.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
describes the definition for the ANA register.
AN Advertisement Register (ANA)
Next page configuration. The local device sets this bit to either request next page transmission or advertise
next page exchange capability.
0 The local device wishes not to engage in next page exchange.
1 The local device has no next pages but wishes to allow reception of next pages. If the local device has no
Reserved. (Ignore on read)
Auto-negotiation complete. This bit is read-only and is cleared by default.
0 Either the auto-negotiation process is underway or the auto-negotiation function is disabled.
1 The auto-negotiation process has completed.
Remote fault. This bit is read-only and is cleared by default. Each read of the status register clears this bit.
0 Normal operation.
1 A remote fault condition was detected. This bit latches high in order for software to detect the condition.
Auto-negotiation ability. While read as set, this bit indicates that the PHY has the ability to perform
auto-negotiation. While read as cleared, this bit indicates the PHY lacks the ability to perform
auto-negotiation. Returns 1 on read. This bit is read-only.
Link status. This bit is read-only and is cleared by default.
0 A valid link is not established. This bit latches low allowing for software polling to detect a failure condition.
1 A valid link is established.
Reserved, should be cleared.
Extended capability. This bit indicates that the PHY contains the extended set of registers (those beyond
control and status). Returns 1 on read. This bit is read-only.
—
1
next pages and the link partner wishes to send next pages, the local device shall send null message
codes and have the message page set to 0b000_0000_0001, as defined in annex 28C.
Remote Fault
2
Figure 15-109. AN Advertisement Register Definition
3
Table 15-113. ANA Field Descriptions
Table 15-112. SR Descriptions
4
—
6
Pause
7
All zeros
Description
Description
8
Duplex
Half
9
Enhanced Three-Speed Ethernet Controllers
Duplex
Full
10
11
Access: Read/Write
—
15-119
15