MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 162

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Reset, Clocking, and Initialization
4.3
This section describes the configuration and control registers that control access to the configuration space
and to the boot code as well as guidelines for accessing these regions. It also contains a brief description
of the boot sequencer which may be used to initialize configuration registers or memory before the CPU
is released to boot.
4.3.1
Table 4-4
In this table and in the register figures and field descriptions, the following access definitions apply:
4.3.1.1
The configuration, control, and status registers are memory mapped. The set of configuration, control, and
status registers occupies a 1-Mbyte region of memory. Their location is programmable using the CCSR base
address register (CCSRBAR). The default base address for the configuration, control, and status registers
is 0xFF70_0000 (CCSRBAR = 0x000F_F700). CCSRBAR itself is part of the local access block of CCSR
memory, which begins at offset 0x0 from CCSRBAR. Because CCSRBAR is at offset 0x0 from the
beginning of the local access registers, CCSRBAR always points to itself. The contents of CCSRBAR are
broadcast internally in the MPC8544E to all functional units that need to be able to identify or create
configuration transactions.
4.3.1.1.1
Updates to CCSRBAR that relocate the entire 1-Mbyte region of configuration, control, and status
registers require special treatment. The effect of the update must be guaranteed to be visible by the
4-4
Local Memory
Offset (Hex)
0x0_0000
0x0_0008
0x0_0010
0x0_0020
•
•
•
•
•
Reserved fields are always ignored for the purposes of determining access type.
R/W, R, and W (read/write, read only, and write only) indicate that all the non-reserved fields in a
register have the same access type.
w1c indicates that all of the non-reserved fields in a register are cleared by writing ones to them.
Mixed indicates a combination of access types.
Special is used when no other category applies. In this case the register figure and field description
table should be read carefully.
Memory Map/Register Definition
shows the memory map for local configuration control registers.
Local Configuration Control
Accessing Configuration, Control, and Status Registers
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Updating CCSRBAR
CCSRBAR—Configuration, control, and status registers base
address register
ALTCBAR—Alternate configuration base address register
ALTCAR—Alternate configuration attribute register
BPTR—Boot page translation register
Table 4-4. Local Configuration Control Register Map
Register
Access
R/W
R/W
R/W
R/W
0x000F_F700
0x0000_0000
0x0000_0000
0x0000_0000
Reset
Freescale Semiconductor
Section/Page
4.3.1.1.2/4-5
4.3.1.2.1/4-6
4.3.1.2.1/4-6
4.3.1.3.1/4-7