MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 820

MPU POWERQUICC III 783-PBGA

MPC8544VTALF

Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8544VTALF

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8544VTALF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC8544VTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Enhanced Three-Speed Ethernet Controllers
15.5.3.6.16 Receive Alignment Error Counter (RALN)
Figure 15-67
Table 15-70
15.5.3.6.17 Receive Frame Length Error Counter (RFLR)
Figure 15-68
Table 15-71
15-88
16–31
16–31
0–15
Bits
0–15
Bits
Offset eTSEC1:0x2_46BC; eTSEC3:0x2_56BC
Reset
Offset eTSEC1:0x2_46C0; eTSEC3:0x2_56C0
Reset
W
W
R
R
Name
RFLR
Name
RALN
0
0
describes the fields of the RALN register.
describes the fields of the RFLR register.
describes the definition for the RALN register.
describes the definition for the RFLR register.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved
Receive frame length error counter. Increments for each frame received in which the 802.3 length field did
not match the number of data bytes actually received (46–1500 bytes). The counter does not increment if
the length field is not a valid 802.3 length, such as an Ethertype value.
Reserved
(VLAN) which contains an invalid FCS and is not an integral number of bytes.
Receive alignment error counter. Increments for each received frame from 64 to 1518 (non VLAN) or 1522
Figure 15-68. Receive Frame Length Error Counter Register Definition
Figure 15-67. Receive Alignment Error Counter Register Definition
Table 15-70. RALN Field Descriptions
Table 15-71. RFLR Field Descriptions
All zeros
All zeros
15 16
15 16
Description
Description
RALN
RFLR
Freescale Semiconductor
Access: Read/Write
Access: Read/Write
31
31

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