MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1181

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
18–20
22–23
27–28
8–14
Bits
15
16
17
21
24
25
26
2
3
4
5
6
7
TSEC1 Three-speed Ethernet controller 1 disable
TSEC3 Three-speed Ethernet controller 3 disable
PCIE1 PCI Express 1 controller disable
PCIE2 PCI Express 2 controller disable
PCIE3 PCI Express 3 controller disable
Name
E500
DMA
DDR
SEC
LBC
TB
—
—
—
—
—
—
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
0 PCI Express 1 controller enable
1 PCI Express 1 controller disable
Reserved
Local bus controller disable
0 Local bus controller enable
1 Local bus controller disable
0 PCI Express 2 controller enable
1 PCI Express 2 controller disable
0 PCI Express 3 controller enable
1 PCI Express 3 controller disable
Security disable
0 Security enable
1 Security disable
Reserved
DDR SDRAM controller disable
0 DDR SDRAM controller enable
1 DDR SDRAM controller disable
e500 core disable
0 e500 core enable
1 e500 core disable. Places the core in the core_stopped state in which it does not respond to interrupts.
For more information, see
Time base (timer facilities) of the e500 core disable
0 Timer facilities enabled
1 Timer facilities disabled.
Reserved
DMA controller disabled
0 DMA controller enabled
1 DMA controller disabled
Reserved
0 eTSEC1 enabled
1 eTSEC1 disabled
Reserved
0 eTSEC3 enabled
1 eTSEC3 disabled
Reserved
Equivalent to nap mode. Instruction fetching is stopped, snooping is disabled, and clocks are shut down to
all functional units of the core including the timer facilities.
Table 19-15. DEVDISR Field Descriptions (continued)
Section 19.5.1.4, “Shutting Down Unused
Description
Blocks.”
Global Utilities
19-15