MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 951

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16.3.1
The following sections describe the DMA registers. The majority of these registers are channel-specific
and can be identified by one of the four offsets that describe the register.
Freescale Semiconductor
0x2C8
Offset
0x28C
0x29C
0x2BC
0x2C0
0x2C4
0x2FC
0x2A0
0x2A4
0x2A8
0x2B0
0x2B4
0x2B8
0x284
0x288
0x290
0x294
0x298
0x300
–
DMA Register Descriptions
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
SR3—DMA 3 status register
ECLNDAR3—DMA 3 current link descriptor extended
address register
CLNDAR3—DMA 3 current link descriptor address register
SATR3—DMA 3 source attributes register
SAR3—DMA 3 source address register
DATR3—DMA 3 destination attributes register
DAR3—DMA 3 destination address register
BCR3—DMA 3 byte count register
ENLNDAR3—DMA 3 next link descriptor extended address
register
NLNDAR3—DMA 3 next link descriptor address register
ECLSDAR3—DMA 3 current list descriptor extended
address register
CLSDAR3—DMA 3 current list descriptor address register
ENLSDAR3—DMA 3 next list descriptor extended address
register
NLSDAR3—DMA 3 next list descriptor address register
SSR3—DMA 3 source stride register
DSR3—DMA 3 destination stride register
Reserved
DGSR—DMA general status register
Table 16-4. DMA Register Summary (continued)
Register
Access
Mixed
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
R
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
—
16.3.1.10/16-21
16.3.1.10/16-21
16.3.1.11/16-22
16.3.1.11/16-22
16.3.1.12/16-22
16.3.1.13/16-23
16.3.1.14/16-24
16.3.1.2/16-12
16.3.1.3/16-13
16.3.1.3/16-13
16.3.1.4/16-15
16.3.1.5/16-16
16.3.1.6/16-17
16.3.1.7/16-18
16.3.1.8/16-19
16.3.1.9/16-19
16.3.1.9/16-19
Section/Page
DMA Controller
—
16-9